include/asm-i386/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <linux/compiler.h>
   8
   9 /*
  10  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  11  *
  12  * Simple spin lock operations.  There are two variants, one clears IRQ's
  13  * on the local processor, one does not.
  14  *
  15  * We make no fairness assumptions. They have a cost.
  16  *
  17  * (the type definitions are in asm/spinlock_types.h)
  18  */
  19
  20 #define __raw_spin_is_locked(x) \
  21                 (*(volatile signed char *)(&(x)->slock) <= 0)
  22
  23 #define __raw_spin_lock_string \
  24         "\n1:\t" \
  25         "lock ; decb %0\n\t" \
  26         "jns 3f\n" \
  27         "2:\t" \
  28         "rep;nop\n\t" \
  29         "cmpb $0,%0\n\t" \
  30         "jle 2b\n\t" \
  31         "jmp 1b\n" \
  32         "3:\n\t"
  33
  34 /*
  35  * NOTE: there's an irqs-on section here, which normally would have to be
  36  * irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use
  37  * __raw_spin_lock_string_flags().
  38  */
  39 #define __raw_spin_lock_string_flags \
  40         "\n1:\t" \
  41         "lock ; decb %0\n\t" \
  42         "jns 5f\n" \
  43         "2:\t" \
  44         "testl $0x200, %1\n\t" \
  45         "jz 4f\n\t" \
  46         "sti\n" \
  47         "3:\t" \
  48         "rep;nop\n\t" \
  49         "cmpb $0, %0\n\t" \
  50         "jle 3b\n\t" \
  51         "cli\n\t" \
  52         "jmp 1b\n" \
  53         "4:\t" \
  54         "rep;nop\n\t" \
  55         "cmpb $0, %0\n\t" \
  56         "jg 1b\n\t" \
  57         "jmp 4b\n" \
  58         "5:\n\t"
  59
  60 #define __raw_spin_lock_string_up \
  61         "\n\tdecb %0"
  62
  63 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  64 {
  65         alternative_smp(
  66                 __raw_spin_lock_string,
  67                 __raw_spin_lock_string_up,
  68                 "+m" (lock->slock) : : "memory");
  69 }
  70
  71 /*
  72  * It is easier for the lock validator if interrupts are not re-enabled
  73  * in the middle of a lock-acquire. This is a performance feature anyway
  74  * so we turn it off:
  75  */
  76 #ifndef CONFIG_PROVE_LOCKING
  77 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
  78 {
  79         alternative_smp(
  80                 __raw_spin_lock_string_flags,
  81                 __raw_spin_lock_string_up,
  82                 "+m" (lock->slock) : "r" (flags) : "memory");
  83 }
  84 #endif
  85
  86 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  87 {
  88         char oldval;
  89         __asm__ __volatile__(
  90                 "xchgb %b0,%1"
  91                 :"=q" (oldval), "+m" (lock->slock)
  92                 :"0" (0) : "memory");
  93         return oldval > 0;
  94 }
  95
  96 /*
  97  * __raw_spin_unlock based on writing $1 to the low byte.
  98  * This method works. Despite all the confusion.
  99  * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
 100  * (PPro errata 66, 92)
 101  */
 102
 103 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
 104
 105 #define __raw_spin_unlock_string \
 106         "movb $1,%0" \
 107                 :"+m" (lock->slock) : : "memory"
 108
 109
 110 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 111 {
 112         __asm__ __volatile__(
 113                 __raw_spin_unlock_string
 114         );
 115 }
 116
 117 #else
 118
 119 #define __raw_spin_unlock_string \
 120         "xchgb %b0, %1" \
 121                 :"=q" (oldval), "+m" (lock->slock) \
 122                 :"0" (oldval) : "memory"
 123
 124 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 125 {
 126         char oldval = 1;
 127
 128         __asm__ __volatile__(
 129                 __raw_spin_unlock_string
 130         );
 131 }
 132
 133 #endif
 134
 135 #define __raw_spin_unlock_wait(lock) \
 136         do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
 137
 138 /*
 139  * Read-write spinlocks, allowing multiple readers
 140  * but only one writer.
 141  *
 142  * NOTE! it is quite common to have readers in interrupts
 143  * but no interrupt writers. For those circumstances we
 144  * can "mix" irq-safe locks - any writer needs to get a
 145  * irq-safe write-lock, but readers can get non-irqsafe
 146  * read-locks.
 147  *
 148  * On x86, we implement read-write locks as a 32-bit counter
 149  * with the high bit (sign) being the "contended" bit.
 150  *
 151  * The inline assembly is non-obvious. Think about it.
 152  *
 153  * Changed to use the same technique as rw semaphores.  See
 154  * semaphore.h for details.  -ben
 155  *
 156  * the helpers are in arch/i386/kernel/semaphore.c
 157  */
 158
 159 /**
 160  * read_can_lock - would read_trylock() succeed?
 161  * @lock: the rwlock in question.
 162  */
 163 #define __raw_read_can_lock(x)          ((int)(x)->lock > 0)
 164
 165 /**
 166  * write_can_lock - would write_trylock() succeed?
 167  * @lock: the rwlock in question.
 168  */
 169 #define __raw_write_can_lock(x)         ((x)->lock == RW_LOCK_BIAS)
 170
 171 static inline void __raw_read_lock(raw_rwlock_t *rw)
 172 {
 173         __build_read_lock(rw, "__read_lock_failed");
 174 }
 175
 176 static inline void __raw_write_lock(raw_rwlock_t *rw)
 177 {
 178         __build_write_lock(rw, "__write_lock_failed");
 179 }
 180
 181 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 182 {
 183         atomic_t *count = (atomic_t *)lock;
 184         atomic_dec(count);
 185         if (atomic_read(count) >= 0)
 186                 return 1;
 187         atomic_inc(count);
 188         return 0;
 189 }
 190
 191 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 192 {
 193         atomic_t *count = (atomic_t *)lock;
 194         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 195                 return 1;
 196         atomic_add(RW_LOCK_BIAS, count);
 197         return 0;
 198 }
 199
 200 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 201 {
 202         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 203 }
 204
 205 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 206 {
 207         asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0"
 208                                  : "+m" (rw->lock) : : "memory");
 209 }
 210
 211 #endif /* __ASM_SPINLOCK_H */