include/asm-i386/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/config.h>
   5 #include <linux/kernel.h>
   6 #include <asm/segment.h>
   7 #include <asm/cpufeature.h>
   8 #include <linux/bitops.h> /* for LOCK_PREFIX */
   9
  10 #ifdef __KERNEL__
  11
  12 struct task_struct;     /* one of the stranger aspects of C forward declarations.. */
  13 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
  14
  15 #define switch_to(prev,next,last) do {                                  \
  16         unsigned long esi,edi;                                          \
  17         asm volatile("pushl %%ebp\n\t"                                  \
  18                      "movl %%esp,%0\n\t"        /* save ESP */          \
  19                      "movl %5,%%esp\n\t"        /* restore ESP */       \
  20                      "movl $1f,%1\n\t"          /* save EIP */          \
  21                      "pushl %6\n\t"             /* restore EIP */       \
  22                      "jmp __switch_to\n"                                \
  23                      "1:\t"                                             \
  24                      "popl %%ebp\n\t"                                   \
  25                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
  26                       "=a" (last),"=S" (esi),"=D" (edi)                 \
  27                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
  28                       "2" (prev), "d" (next));                          \
  29 } while (0)
  30
  31 #define _set_base(addr,base) do { unsigned long __pr; \
  32 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  33         "rorl $16,%%edx\n\t" \
  34         "movb %%dl,%2\n\t" \
  35         "movb %%dh,%3" \
  36         :"=&d" (__pr) \
  37         :"m" (*((addr)+2)), \
  38          "m" (*((addr)+4)), \
  39          "m" (*((addr)+7)), \
  40          "0" (base) \
  41         ); } while(0)
  42
  43 #define _set_limit(addr,limit) do { unsigned long __lr; \
  44 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  45         "rorl $16,%%edx\n\t" \
  46         "movb %2,%%dh\n\t" \
  47         "andb $0xf0,%%dh\n\t" \
  48         "orb %%dh,%%dl\n\t" \
  49         "movb %%dl,%2" \
  50         :"=&d" (__lr) \
  51         :"m" (*(addr)), \
  52          "m" (*((addr)+6)), \
  53          "0" (limit) \
  54         ); } while(0)
  55
  56 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
  57 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1)>>12 )
  58
  59 static inline unsigned long _get_base(char * addr)
  60 {
  61         unsigned long __base;
  62         __asm__("movb %3,%%dh\n\t"
  63                 "movb %2,%%dl\n\t"
  64                 "shll $16,%%edx\n\t"
  65                 "movw %1,%%dx"
  66                 :"=&d" (__base)
  67                 :"m" (*((addr)+2)),
  68                  "m" (*((addr)+4)),
  69                  "m" (*((addr)+7)));
  70         return __base;
  71 }
  72
  73 #define get_base(ldt) _get_base( ((char *)&(ldt)) )
  74
  75 /*
  76  * Load a segment. Fall back on loading the zero
  77  * segment if something goes wrong..
  78  */
  79 #define loadsegment(seg,value)                  \
  80         asm volatile("\n"                       \
  81                 "1:\t"                          \
  82                 "mov %0,%%" #seg "\n"           \
  83                 "2:\n"                          \
  84                 ".section .fixup,\"ax\"\n"      \
  85                 "3:\t"                          \
  86                 "pushl $0\n\t"                  \
  87                 "popl %%" #seg "\n\t"           \
  88                 "jmp 2b\n"                      \
  89                 ".previous\n"                   \
  90                 ".section __ex_table,\"a\"\n\t" \
  91                 ".align 4\n\t"                  \
  92                 ".long 1b,3b\n"                 \
  93                 ".previous"                     \
  94                 : :"rm" (value))
  95
  96 /*
  97  * Save a segment register away
  98  */
  99 #define savesegment(seg, value) \
 100         asm volatile("mov %%" #seg ",%0":"=rm" (value))
 101
 102 /*
 103  * Clear and set 'TS' bit respectively
 104  */
 105 #define clts() __asm__ __volatile__ ("clts")
 106 #define read_cr0() ({ \
 107         unsigned int __dummy; \
 108         __asm__ __volatile__( \
 109                 "movl %%cr0,%0\n\t" \
 110                 :"=r" (__dummy)); \
 111         __dummy; \
 112 })
 113 #define write_cr0(x) \
 114         __asm__ __volatile__("movl %0,%%cr0": :"r" (x));
 115
 116 #define read_cr2() ({ \
 117         unsigned int __dummy; \
 118         __asm__ __volatile__( \
 119                 "movl %%cr2,%0\n\t" \
 120                 :"=r" (__dummy)); \
 121         __dummy; \
 122 })
 123 #define write_cr2(x) \
 124         __asm__ __volatile__("movl %0,%%cr2": :"r" (x));
 125
 126 #define read_cr3() ({ \
 127         unsigned int __dummy; \
 128         __asm__ ( \
 129                 "movl %%cr3,%0\n\t" \
 130                 :"=r" (__dummy)); \
 131         __dummy; \
 132 })
 133 #define write_cr3(x) \
 134         __asm__ __volatile__("movl %0,%%cr3": :"r" (x));
 135
 136 #define read_cr4() ({ \
 137         unsigned int __dummy; \
 138         __asm__( \
 139                 "movl %%cr4,%0\n\t" \
 140                 :"=r" (__dummy)); \
 141         __dummy; \
 142 })
 143 #define write_cr4(x) \
 144         __asm__ __volatile__("movl %0,%%cr4": :"r" (x));
 145 #define stts() write_cr0(8 | read_cr0())
 146
 147 #endif  /* __KERNEL__ */
 148
 149 #define wbinvd() \
 150         __asm__ __volatile__ ("wbinvd": : :"memory");
 151
 152 static inline unsigned long get_limit(unsigned long segment)
 153 {
 154         unsigned long __limit;
 155         __asm__("lsll %1,%0"
 156                 :"=r" (__limit):"r" (segment));
 157         return __limit+1;
 158 }
 159
 160 #define nop() __asm__ __volatile__ ("nop")
 161
 162 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 163
 164 #define tas(ptr) (xchg((ptr),1))
 165
 166 struct __xchg_dummy { unsigned long a[100]; };
 167 #define __xg(x) ((struct __xchg_dummy *)(x))
 168
 169
 170 #ifdef CONFIG_X86_CMPXCHG64
 171
 172 /*
 173  * The semantics of XCHGCMP8B are a bit strange, this is why
 174  * there is a loop and the loading of %%eax and %%edx has to
 175  * be inside. This inlines well in most cases, the cached
 176  * cost is around ~38 cycles. (in the future we might want
 177  * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
 178  * might have an implicit FPU-save as a cost, so it's not
 179  * clear which path to go.)
 180  *
 181  * cmpxchg8b must be used with the lock prefix here to allow
 182  * the instruction to be executed atomically, see page 3-102
 183  * of the instruction set reference 24319102.pdf. We need
 184  * the reader side to see the coherent 64bit value.
 185  */
 186 static inline void __set_64bit (unsigned long long * ptr,
 187                 unsigned int low, unsigned int high)
 188 {
 189         __asm__ __volatile__ (
 190                 "\n1:\t"
 191                 "movl (%0), %%eax\n\t"
 192                 "movl 4(%0), %%edx\n\t"
 193                 "lock cmpxchg8b (%0)\n\t"
 194                 "jnz 1b"
 195                 : /* no outputs */
 196                 :       "D"(ptr),
 197                         "b"(low),
 198                         "c"(high)
 199                 :       "ax","dx","memory");
 200 }
 201
 202 static inline void __set_64bit_constant (unsigned long long *ptr,
 203                                                  unsigned long long value)
 204 {
 205         __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
 206 }
 207 #define ll_low(x)       *(((unsigned int*)&(x))+0)
 208 #define ll_high(x)      *(((unsigned int*)&(x))+1)
 209
 210 static inline void __set_64bit_var (unsigned long long *ptr,
 211                          unsigned long long value)
 212 {
 213         __set_64bit(ptr,ll_low(value), ll_high(value));
 214 }
 215
 216 #define set_64bit(ptr,value) \
 217 (__builtin_constant_p(value) ? \
 218  __set_64bit_constant(ptr, value) : \
 219  __set_64bit_var(ptr, value) )
 220
 221 #define _set_64bit(ptr,value) \
 222 (__builtin_constant_p(value) ? \
 223  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
 224  __set_64bit(ptr, ll_low(value), ll_high(value)) )
 225
 226 #endif
 227
 228 /*
 229  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 230  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 231  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 232  */
 233 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 234 {
 235         switch (size) {
 236                 case 1:
 237                         __asm__ __volatile__("xchgb %b0,%1"
 238                                 :"=q" (x)
 239                                 :"m" (*__xg(ptr)), "0" (x)
 240                                 :"memory");
 241                         break;
 242                 case 2:
 243                         __asm__ __volatile__("xchgw %w0,%1"
 244                                 :"=r" (x)
 245                                 :"m" (*__xg(ptr)), "0" (x)
 246                                 :"memory");
 247                         break;
 248                 case 4:
 249                         __asm__ __volatile__("xchgl %0,%1"
 250                                 :"=r" (x)
 251                                 :"m" (*__xg(ptr)), "0" (x)
 252                                 :"memory");
 253                         break;
 254         }
 255         return x;
 256 }
 257
 258 /*
 259  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 260  * store NEW in MEM.  Return the initial value in MEM.  Success is
 261  * indicated by comparing RETURN with OLD.
 262  */
 263
 264 #ifdef CONFIG_X86_CMPXCHG
 265 #define __HAVE_ARCH_CMPXCHG 1
 266
 267 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 268                                       unsigned long new, int size)
 269 {
 270         unsigned long prev;
 271         switch (size) {
 272         case 1:
 273                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 274                                      : "=a"(prev)
 275                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 276                                      : "memory");
 277                 return prev;
 278         case 2:
 279                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 280                                      : "=a"(prev)
 281                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 282                                      : "memory");
 283                 return prev;
 284         case 4:
 285                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
 286                                      : "=a"(prev)
 287                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 288                                      : "memory");
 289                 return prev;
 290         }
 291         return old;
 292 }
 293
 294 #define cmpxchg(ptr,o,n)\
 295         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 296                                         (unsigned long)(n),sizeof(*(ptr))))
 297
 298 #endif
 299
 300 #ifdef CONFIG_X86_CMPXCHG64
 301
 302 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
 303                                       unsigned long long new)
 304 {
 305         unsigned long long prev;
 306         __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
 307                              : "=A"(prev)
 308                              : "b"((unsigned long)new),
 309                                "c"((unsigned long)(new >> 32)),
 310                                "m"(*__xg(ptr)),
 311                                "0"(old)
 312                              : "memory");
 313         return prev;
 314 }
 315
 316 #define cmpxchg64(ptr,o,n)\
 317         ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
 318                                         (unsigned long long)(n)))
 319
 320 #endif
 321
 322 #ifdef __KERNEL__
 323 struct alt_instr {
 324         __u8 *instr;            /* original instruction */
 325         __u8 *replacement;
 326         __u8  cpuid;            /* cpuid bit set for replacement */
 327         __u8  instrlen;         /* length of original instruction */
 328         __u8  replacementlen;   /* length of new instruction, <= instrlen */
 329         __u8  pad;
 330 };
 331 #endif
 332
 333 /*
 334  * Alternative instructions for different CPU types or capabilities.
 335  *
 336  * This allows to use optimized instructions even on generic binary
 337  * kernels.
 338  *
 339  * length of oldinstr must be longer or equal the length of newinstr
 340  * It can be padded with nops as needed.
 341  *
 342  * For non barrier like inlines please define new variants
 343  * without volatile and memory clobber.
 344  */
 345 #define alternative(oldinstr, newinstr, feature)        \
 346         asm volatile ("661:\n\t" oldinstr "\n662:\n"                 \
 347                       ".section .altinstructions,\"a\"\n"            \
 348                       "  .align 4\n"                                   \
 349                       "  .long 661b\n"            /* label */          \
 350                       "  .long 663f\n"            /* new instruction */         \
 351                       "  .byte %c0\n"             /* feature bit */    \
 352                       "  .byte 662b-661b\n"       /* sourcelen */      \
 353                       "  .byte 664f-663f\n"       /* replacementlen */ \
 354                       ".previous\n"                                             \
 355                       ".section .altinstr_replacement,\"ax\"\n"                 \
 356                       "663:\n\t" newinstr "\n664:\n"   /* replacement */    \
 357                       ".previous" :: "i" (feature) : "memory")
 358
 359 /*
 360  * Alternative inline assembly with input.
 361  *
 362  * Pecularities:
 363  * No memory clobber here.
 364  * Argument numbers start with 1.
 365  * Best is to use constraints that are fixed size (like (%1) ... "r")
 366  * If you use variable sized constraints like "m" or "g" in the
 367  * replacement maake sure to pad to the worst case length.
 368  */
 369 #define alternative_input(oldinstr, newinstr, feature, input...)                \
 370         asm volatile ("661:\n\t" oldinstr "\n662:\n"                            \
 371                       ".section .altinstructions,\"a\"\n"                       \
 372                       "  .align 4\n"                                            \
 373                       "  .long 661b\n"            /* label */                   \
 374                       "  .long 663f\n"            /* new instruction */         \
 375                       "  .byte %c0\n"             /* feature bit */             \
 376                       "  .byte 662b-661b\n"       /* sourcelen */               \
 377                       "  .byte 664f-663f\n"       /* replacementlen */          \
 378                       ".previous\n"                                             \
 379                       ".section .altinstr_replacement,\"ax\"\n"                 \
 380                       "663:\n\t" newinstr "\n664:\n"   /* replacement */        \
 381                       ".previous" :: "i" (feature), ##input)
 382
 383 /*
 384  * Force strict CPU ordering.
 385  * And yes, this is required on UP too when we're talking
 386  * to devices.
 387  *
 388  * For now, "wmb()" doesn't actually do anything, as all
 389  * Intel CPU's follow what Intel calls a *Processor Order*,
 390  * in which all writes are seen in the program order even
 391  * outside the CPU.
 392  *
 393  * I expect future Intel CPU's to have a weaker ordering,
 394  * but I'd also expect them to finally get their act together
 395  * and add some real memory barriers if so.
 396  *
 397  * Some non intel clones support out of order store. wmb() ceases to be a
 398  * nop for these.
 399  */
 400
 401
 402 /*
 403  * Actually only lfence would be needed for mb() because all stores done
 404  * by the kernel should be already ordered. But keep a full barrier for now.
 405  */
 406
 407 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 408 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 409
 410 /**
 411  * read_barrier_depends - Flush all pending reads that subsequents reads
 412  * depend on.
 413  *
 414  * No data-dependent reads from memory-like regions are ever reordered
 415  * over this barrier.  All reads preceding this primitive are guaranteed
 416  * to access memory (but not necessarily other CPUs' caches) before any
 417  * reads following this primitive that depend on the data return by
 418  * any of the preceding reads.  This primitive is much lighter weight than
 419  * rmb() on most CPUs, and is never heavier weight than is
 420  * rmb().
 421  *
 422  * These ordering constraints are respected by both the local CPU
 423  * and the compiler.
 424  *
 425  * Ordering is not guaranteed by anything other than these primitives,
 426  * not even by data dependencies.  See the documentation for
 427  * memory_barrier() for examples and URLs to more information.
 428  *
 429  * For example, the following code would force ordering (the initial
 430  * value of "a" is zero, "b" is one, and "p" is "&a"):
 431  *
 432  * <programlisting>
 433  *      CPU 0                           CPU 1
 434  *
 435  *      b = 2;
 436  *      memory_barrier();
 437  *      p = &b;                         q = p;
 438  *                                      read_barrier_depends();
 439  *                                      d = *q;
 440  * </programlisting>
 441  *
 442  * because the read of "*q" depends on the read of "p" and these
 443  * two reads are separated by a read_barrier_depends().  However,
 444  * the following code, with the same initial values for "a" and "b":
 445  *
 446  * <programlisting>
 447  *      CPU 0                           CPU 1
 448  *
 449  *      a = 2;
 450  *      memory_barrier();
 451  *      b = 3;                          y = b;
 452  *                                      read_barrier_depends();
 453  *                                      x = a;
 454  * </programlisting>
 455  *
 456  * does not enforce ordering, since there is no data dependency between
 457  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 458  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 459  * in cases like thiswhere there are no data dependencies.
 460  **/
 461
 462 #define read_barrier_depends()  do { } while(0)
 463
 464 #ifdef CONFIG_X86_OOSTORE
 465 /* Actually there are no OOO store capable CPUs for now that do SSE,
 466    but make it already an possibility. */
 467 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 468 #else
 469 #define wmb()   __asm__ __volatile__ ("": : :"memory")
 470 #endif
 471
 472 #ifdef CONFIG_SMP
 473 #define smp_mb()        mb()
 474 #define smp_rmb()       rmb()
 475 #define smp_wmb()       wmb()
 476 #define smp_read_barrier_depends()      read_barrier_depends()
 477 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 478 #else
 479 #define smp_mb()        barrier()
 480 #define smp_rmb()       barrier()
 481 #define smp_wmb()       barrier()
 482 #define smp_read_barrier_depends()      do { } while(0)
 483 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 484 #endif
 485
 486 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 487
 488 /* interrupt control.. */
 489 #define local_save_flags(x)     do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
 490 #define local_irq_restore(x)    do { typecheck(unsigned long,x); __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc"); } while (0)
 491 #define local_irq_disable()     __asm__ __volatile__("cli": : :"memory")
 492 #define local_irq_enable()      __asm__ __volatile__("sti": : :"memory")
 493 /* used in the idle loop; sti takes one instruction cycle to complete */
 494 #define safe_halt()             __asm__ __volatile__("sti; hlt": : :"memory")
 495 /* used when interrupts are already enabled or to shutdown the processor */
 496 #define halt()                  __asm__ __volatile__("hlt": : :"memory")
 497
 498 #define irqs_disabled()                 \
 499 ({                                      \
 500         unsigned long flags;            \
 501         local_save_flags(flags);        \
 502         !(flags & (1<<9));              \
 503 })
 504
 505 /* For spinlocks etc */
 506 #define local_irq_save(x)       __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
 507
 508 /*
 509  * disable hlt during certain critical i/o operations
 510  */
 511 #define HAVE_DISABLE_HLT
 512 void disable_hlt(void);
 513 void enable_hlt(void);
 514
 515 extern int es7000_plat;
 516 void cpu_idle_wait(void);
 517
 518 extern unsigned long arch_align_stack(unsigned long sp);
 519
 520 #endif