include/asm-ia64/sn/addrs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved.
   7  */
   8
   9 #ifndef _ASM_IA64_SN_ADDRS_H
  10 #define _ASM_IA64_SN_ADDRS_H
  11
  12 #include <asm/percpu.h>
  13 #include <asm/sn/types.h>
  14 #include <asm/sn/arch.h>
  15 #include <asm/sn/pda.h>
  16
  17 /*
  18  *  Memory/SHUB Address Format:
  19  *  +-+---------+--+--------------+
  20  *  |0|  NASID  |AS| NodeOffset   |
  21  *  +-+---------+--+--------------+
  22  *
  23  *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
  24  *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
  25  *     00: Local Resources and MMR space
  26  *           Top bit of NodeOffset
  27  *               0: Local resources space
  28  *                  node id:
  29  *                        0: IA64/NT compatibility space
  30  *                        2: Local MMR Space
  31  *                        4: Local memory, regardless of local node id
  32  *               1: Global MMR space
  33  *     01: GET space.
  34  *     10: AMO space.
  35  *     11: Cacheable memory space.
  36  *
  37  *   NodeOffset: byte offset
  38  *
  39  *
  40  *  TIO address format:
  41  *  +-+----------+--+--------------+
  42  *  |0|  NASID   |AS| Nodeoffset   |
  43  *  +-+----------+--+--------------+
  44  *
  45  *  NASID: (low NASID bit is 1) TIO
  46  *   AS: 2-bit Chiplet Identifier
  47  *     00: TIO LB (Indicates TIO MMR access.)
  48  *     01: TIO ICE (indicates coretalk space access.)
  49  *
  50  *   NodeOffset: top bit must be set.
  51  *
  52  *
  53  * Note that in both of the above address formats, the low
  54  * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
  55  */
  56
  57
  58 /*
  59  * Define basic shift & mask constants for manipulating NASIDs and AS values.
  60  */
  61 #define NASID_BITMASK           (sn_hub_info->nasid_bitmask)
  62 #define NASID_SHIFT             (sn_hub_info->nasid_shift)
  63 #define AS_SHIFT                (sn_hub_info->as_shift)
  64 #define AS_BITMASK              0x3UL
  65
  66 #define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
  67 #define AS_MASK                 ((u64)AS_BITMASK << AS_SHIFT)
  68 #define REGION_BITS             0xe000000000000000UL
  69
  70
  71 /*
  72  * AS values. These are the same on both SHUB1 & SHUB2.
  73  */
  74 #define AS_GET_VAL              1UL
  75 #define AS_AMO_VAL              2UL
  76 #define AS_CAC_VAL              3UL
  77 #define AS_GET_SPACE            (AS_GET_VAL << AS_SHIFT)
  78 #define AS_AMO_SPACE            (AS_AMO_VAL << AS_SHIFT)
  79 #define AS_CAC_SPACE            (AS_CAC_VAL << AS_SHIFT)
  80
  81
  82 /*
  83  * Base addresses for various address ranges.
  84  */
  85 #define CACHED                  0xe000000000000000UL
  86 #define UNCACHED                0xc000000000000000UL
  87 #define UNCACHED_PHYS           0x8000000000000000UL
  88
  89
  90 /*
  91  * Virtual Mode Local & Global MMR space.
  92  */
  93 #define SH1_LOCAL_MMR_OFFSET    0x8000000000UL
  94 #define SH2_LOCAL_MMR_OFFSET    0x0200000000UL
  95 #define LOCAL_MMR_OFFSET        (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
  96 #define LOCAL_MMR_SPACE         (UNCACHED | LOCAL_MMR_OFFSET)
  97 #define LOCAL_PHYS_MMR_SPACE    (UNCACHED_PHYS | LOCAL_MMR_OFFSET)
  98
  99 #define SH1_GLOBAL_MMR_OFFSET   0x0800000000UL
 100 #define SH2_GLOBAL_MMR_OFFSET   0x0300000000UL
 101 #define GLOBAL_MMR_OFFSET       (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
 102 #define GLOBAL_MMR_SPACE        (UNCACHED | GLOBAL_MMR_OFFSET)
 103
 104 /*
 105  * Physical mode addresses
 106  */
 107 #define GLOBAL_PHYS_MMR_SPACE   (UNCACHED_PHYS | GLOBAL_MMR_OFFSET)
 108
 109
 110 /*
 111  * Clear region & AS bits.
 112  */
 113 #define TO_PHYS_MASK            (~(REGION_BITS | AS_MASK))
 114
 115
 116 /*
 117  * Misc NASID manipulation.
 118  */
 119 #define NASID_SPACE(n)          ((u64)(n) << NASID_SHIFT)
 120 #define REMOTE_ADDR(n,a)        (NASID_SPACE(n) | (a))
 121 #define NODE_OFFSET(x)          ((x) & (NODE_ADDRSPACE_SIZE - 1))
 122 #define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
 123 #define NASID_GET(x)            (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
 124 #define LOCAL_MMR_ADDR(a)       (LOCAL_MMR_SPACE | (a))
 125 #define GLOBAL_MMR_ADDR(n,a)    (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
 126 #define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
 127 #define GLOBAL_CAC_ADDR(n,a)    (CAC_BASE | REMOTE_ADDR(n,a))
 128 #define CHANGE_NASID(n,x)       ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
 129
 130
 131 /* non-II mmr's start at top of big window space (4G) */
 132 #define BWIN_TOP                0x0000000100000000UL
 133
 134 /*
 135  * general address defines
 136  */
 137 #define CAC_BASE                (CACHED   | AS_CAC_SPACE)
 138 #define AMO_BASE                (UNCACHED | AS_AMO_SPACE)
 139 #define GET_BASE                (CACHED   | AS_GET_SPACE)
 140
 141 /*
 142  * Convert Memory addresses between various addressing modes.
 143  */
 144 #define TO_PHYS(x)              (TO_PHYS_MASK & (x))
 145 #define TO_CAC(x)               (CAC_BASE     | TO_PHYS(x))
 146 #define TO_AMO(x)               (AMO_BASE     | TO_PHYS(x))
 147 #define TO_GET(x)               (GET_BASE     | TO_PHYS(x))
 148
 149
 150 /*
 151  * Covert from processor physical address to II/TIO physical address:
 152  *      II - squeeze out the AS bits
 153  *      TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
 154  *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
 155  *           to insert a chiplet id into this macro.  However, it is our belief
 156  *           right now that this chiplet id will be ICE, which is also zero.
 157  */
 158 #define PHYS_TO_TIODMA(x)       ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x))
 159 #define PHYS_TO_DMA(x)          ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
 160
 161
 162 /*
 163  * The following definitions pertain to the IO special address
 164  * space.  They define the location of the big and little windows
 165  * of any given node.
 166  */
 167 #define BWIN_SIZE_BITS                  29      /* big window size: 512M */
 168 #define TIO_BWIN_SIZE_BITS              30      /* big window size: 1G */
 169 #define NODE_SWIN_BASE(n, w)            ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
 170                 : RAW_NODE_SWIN_BASE(n, w))
 171 #define NODE_IO_BASE(n)                 (GLOBAL_MMR_SPACE | NASID_SPACE(n))
 172 #define BWIN_SIZE                       (1UL << BWIN_SIZE_BITS)
 173 #define NODE_BWIN_BASE0(n)              (NODE_IO_BASE(n) + BWIN_SIZE)
 174 #define NODE_BWIN_BASE(n, w)            (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
 175 #define RAW_NODE_SWIN_BASE(n, w)        (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
 176 #define BWIN_WIDGET_MASK                0x7
 177 #define BWIN_WINDOWNUM(x)               (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
 178
 179 #define TIO_BWIN_WINDOW_SELECT_MASK     0x7
 180 #define TIO_BWIN_WINDOWNUM(x)           (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
 181
 182
 183
 184 /*
 185  * The following definitions pertain to the IO special address
 186  * space.  They define the location of the big and little windows
 187  * of any given node.
 188  */
 189
 190 #define SWIN_SIZE_BITS                  24
 191 #define SWIN_WIDGET_MASK                0xF
 192
 193 #define TIO_SWIN_SIZE_BITS              28
 194 #define TIO_SWIN_SIZE                   (1UL << TIO_SWIN_SIZE_BITS)
 195 #define TIO_SWIN_WIDGET_MASK            0x3
 196
 197 /*
 198  * Convert smallwindow address to xtalk address.
 199  *
 200  * 'addr' can be physical or virtual address, but will be converted
 201  * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
 202  */
 203 #define SWIN_WIDGETNUM(x)               (((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
 204 #define TIO_SWIN_WIDGETNUM(x)           (((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
 205
 206
 207 /*
 208  * The following macros produce the correct base virtual address for
 209  * the hub registers. The REMOTE_HUB_* macro produce
 210  * the address for the specified hub's registers.  The intent is
 211  * that the appropriate PI, MD, NI, or II register would be substituted
 212  * for x.
 213  *
 214  *   WARNING:
 215  *      When certain Hub chip workaround are defined, it's not sufficient
 216  *      to dereference the *_HUB_ADDR() macros.  You should instead use
 217  *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
 218  *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
 219  *      They're always safe.
 220  */
 221 #define REMOTE_HUB_ADDR(n,x)                                            \
 222         ((n & 1) ?                                                      \
 223         /* TIO: */                                                      \
 224         ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))                        \
 225         : /* SHUB: */                                                   \
 226         (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\
 227         : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
 228
 229
 230
 231 #define HUB_L(x)                        (*((volatile typeof(*x) *)x))
 232 #define HUB_S(x,d)                      (*((volatile typeof(*x) *)x) = (d))
 233
 234 #define REMOTE_HUB_L(n, a)              HUB_L(REMOTE_HUB_ADDR((n), (a)))
 235 #define REMOTE_HUB_S(n, a, d)           HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
 236
 237
 238 #endif /* _ASM_IA64_SN_ADDRS_H */