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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - include/asm-m68knommu/dma.h
10 * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
11 * address mode emits a source address, and expects that the device will either
12 * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
13 * the device will place data on the correct byte(s) of the data bus, as the
14 * memory transactions are always 32 bits. This implies that only 32 bit
15 * devices will find single mode transfers useful. Dual address DMA mode
16 * performs two cycles: source read and destination write. ColdFire will
17 * align the data so that the device will always get the correct bytes, thus
18 * is useful for 8 and 16 bit devices. This is the mode that is supported
21 * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
22 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
24 * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
25 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
27 * APR/18/2002 : added proper support for MCF5272 DMA controller.
28 * Arthur Shipkowski (art@videon-central.com)
31 #include <asm/coldfire.h>
32 #include <asm/mcfsim.h>
33 #include <asm/mcfdma.h>
36 * Set number of channels of DMA on ColdFire for different implementations.
38 #if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
39 #define MAX_M68K_DMA_CHANNELS 4
40 #elif defined(CONFIG_M5272)
41 #define MAX_M68K_DMA_CHANNELS 1
42 #elif defined(CONFIG_M532x)
43 #define MAX_M68K_DMA_CHANNELS 0
45 #define MAX_M68K_DMA_CHANNELS 2
48 extern unsigned int dma_base_addr
[MAX_M68K_DMA_CHANNELS
];
49 extern unsigned int dma_device_address
[MAX_M68K_DMA_CHANNELS
];
51 #if !defined(CONFIG_M5272)
52 #define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
53 #define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
54 #define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
55 #define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
57 /* I/O to memory, 8 bits, mode */
58 #define DMA_MODE_READ 0
59 /* memory to I/O, 8 bits, mode */
60 #define DMA_MODE_WRITE 1
61 /* I/O to memory, 16 bits, mode */
62 #define DMA_MODE_READ_WORD 2
63 /* memory to I/O, 16 bits, mode */
64 #define DMA_MODE_WRITE_WORD 3
65 /* I/O to memory, 32 bits, mode */
66 #define DMA_MODE_READ_LONG 4
67 /* memory to I/O, 32 bits, mode */
68 #define DMA_MODE_WRITE_LONG 5
69 /* I/O to memory, 8 bits, single-address-mode */
70 #define DMA_MODE_READ_SINGLE 8
71 /* memory to I/O, 8 bits, single-address-mode */
72 #define DMA_MODE_WRITE_SINGLE 9
73 /* I/O to memory, 16 bits, single-address-mode */
74 #define DMA_MODE_READ_WORD_SINGLE 10
75 /* memory to I/O, 16 bits, single-address-mode */
76 #define DMA_MODE_WRITE_WORD_SINGLE 11
77 /* I/O to memory, 32 bits, single-address-mode */
78 #define DMA_MODE_READ_LONG_SINGLE 12
79 /* memory to I/O, 32 bits, single-address-mode */
80 #define DMA_MODE_WRITE_LONG_SINGLE 13
82 #else /* CONFIG_M5272 is defined */
84 /* Source static-address mode */
85 #define DMA_MODE_SRC_SA_BIT 0x01
86 /* Two bits to select between all four modes */
87 #define DMA_MODE_SSIZE_MASK 0x06
88 /* Offset to shift bits in */
89 #define DMA_MODE_SSIZE_OFF 0x01
90 /* Destination static-address mode */
91 #define DMA_MODE_DES_SA_BIT 0x10
92 /* Two bits to select between all four modes */
93 #define DMA_MODE_DSIZE_MASK 0x60
94 /* Offset to shift bits in */
95 #define DMA_MODE_DSIZE_OFF 0x05
97 #define DMA_MODE_SIZE_LONG 0x00
98 #define DMA_MODE_SIZE_BYTE 0x01
99 #define DMA_MODE_SIZE_WORD 0x02
100 #define DMA_MODE_SIZE_LINE 0x03
103 * Aliases to help speed quick ports; these may be suboptimal, however. They
104 * do not include the SINGLE mode modifiers since the MCF5272 does not have a
105 * mode where the device is in control of its addressing.
108 /* I/O to memory, 8 bits, mode */
109 #define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
110 /* memory to I/O, 8 bits, mode */
111 #define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
112 /* I/O to memory, 16 bits, mode */
113 #define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
114 /* memory to I/O, 16 bits, mode */
115 #define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
116 /* I/O to memory, 32 bits, mode */
117 #define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
118 /* memory to I/O, 32 bits, mode */
119 #define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
121 #endif /* !defined(CONFIG_M5272) */
123 #if !defined(CONFIG_M5272)
124 /* enable/disable a specific DMA channel */
125 static __inline__
void enable_dma(unsigned int dmanr
)
127 volatile unsigned short *dmawp
;
130 printk("enable_dma(dmanr=%d)\n", dmanr
);
133 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
134 dmawp
[MCFDMA_DCR
] |= MCFDMA_DCR_EEXT
;
137 static __inline__
void disable_dma(unsigned int dmanr
)
139 volatile unsigned short *dmawp
;
140 volatile unsigned char *dmapb
;
143 printk("disable_dma(dmanr=%d)\n", dmanr
);
146 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
147 dmapb
= (unsigned char *) dma_base_addr
[dmanr
];
149 /* Turn off external requests, and stop any DMA in progress */
150 dmawp
[MCFDMA_DCR
] &= ~MCFDMA_DCR_EEXT
;
151 dmapb
[MCFDMA_DSR
] = MCFDMA_DSR_DONE
;
155 * Clear the 'DMA Pointer Flip Flop'.
156 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
157 * Use this once to initialize the FF to a known state.
158 * After that, keep track of it. :-)
159 * --- In order to do that, the DMA routines below should ---
160 * --- only be used while interrupts are disabled! ---
162 * This is a NOP for ColdFire. Provide a stub for compatibility.
164 static __inline__
void clear_dma_ff(unsigned int dmanr
)
168 /* set mode (above) for a specific DMA channel */
169 static __inline__
void set_dma_mode(unsigned int dmanr
, char mode
)
172 volatile unsigned char *dmabp
;
173 volatile unsigned short *dmawp
;
176 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr
, mode
);
179 dmabp
= (unsigned char *) dma_base_addr
[dmanr
];
180 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
182 // Clear config errors
183 dmabp
[MCFDMA_DSR
] = MCFDMA_DSR_DONE
;
185 // Set command register
187 MCFDMA_DCR_INT
| // Enable completion irq
188 MCFDMA_DCR_CS
| // Force one xfer per request
189 MCFDMA_DCR_AA
| // Enable auto alignment
190 // single-address-mode
191 ((mode
& DMA_MODE_SINGLE_BIT
) ? MCFDMA_DCR_SAA
: 0) |
192 // sets s_rw (-> r/w) high if Memory to I/0
193 ((mode
& DMA_MODE_WRITE_BIT
) ? MCFDMA_DCR_S_RW
: 0) |
194 // Memory to I/O or I/O to Memory
195 ((mode
& DMA_MODE_WRITE_BIT
) ? MCFDMA_DCR_SINC
: MCFDMA_DCR_DINC
) |
196 // 32 bit, 16 bit or 8 bit transfers
197 ((mode
& DMA_MODE_WORD_BIT
) ? MCFDMA_DCR_SSIZE_WORD
:
198 ((mode
& DMA_MODE_LONG_BIT
) ? MCFDMA_DCR_SSIZE_LONG
:
199 MCFDMA_DCR_SSIZE_BYTE
)) |
200 ((mode
& DMA_MODE_WORD_BIT
) ? MCFDMA_DCR_DSIZE_WORD
:
201 ((mode
& DMA_MODE_LONG_BIT
) ? MCFDMA_DCR_DSIZE_LONG
:
202 MCFDMA_DCR_DSIZE_BYTE
));
205 printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__
, __LINE__
,
206 dmanr
, (int) &dmabp
[MCFDMA_DSR
], dmabp
[MCFDMA_DSR
],
207 (int) &dmawp
[MCFDMA_DCR
], dmawp
[MCFDMA_DCR
]);
211 /* Set transfer address for specific DMA channel */
212 static __inline__
void set_dma_addr(unsigned int dmanr
, unsigned int a
)
214 volatile unsigned short *dmawp
;
215 volatile unsigned int *dmalp
;
218 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
221 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
222 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
224 // Determine which address registers are used for memory/device accesses
225 if (dmawp
[MCFDMA_DCR
] & MCFDMA_DCR_SINC
) {
226 // Source incrementing, must be memory
227 dmalp
[MCFDMA_SAR
] = a
;
228 // Set dest address, must be device
229 dmalp
[MCFDMA_DAR
] = dma_device_address
[dmanr
];
231 // Destination incrementing, must be memory
232 dmalp
[MCFDMA_DAR
] = a
;
233 // Set source address, must be device
234 dmalp
[MCFDMA_SAR
] = dma_device_address
[dmanr
];
238 printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
239 __FILE__
, __LINE__
, dmanr
, (int) &dmawp
[MCFDMA_DCR
], dmawp
[MCFDMA_DCR
],
240 (int) &dmalp
[MCFDMA_SAR
], dmalp
[MCFDMA_SAR
],
241 (int) &dmalp
[MCFDMA_DAR
], dmalp
[MCFDMA_DAR
]);
246 * Specific for Coldfire - sets device address.
247 * Should be called after the mode set call, and before set DMA address.
249 static __inline__
void set_dma_device_addr(unsigned int dmanr
, unsigned int a
)
252 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
255 dma_device_address
[dmanr
] = a
;
259 * NOTE 2: "count" represents _bytes_.
261 static __inline__
void set_dma_count(unsigned int dmanr
, unsigned int count
)
263 volatile unsigned short *dmawp
;
266 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr
, count
);
269 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
270 dmawp
[MCFDMA_BCR
] = (unsigned short)count
;
274 * Get DMA residue count. After a DMA transfer, this
275 * should return zero. Reading this while a DMA transfer is
276 * still in progress will return unpredictable results.
277 * Otherwise, it returns the number of _bytes_ left to transfer.
279 static __inline__
int get_dma_residue(unsigned int dmanr
)
281 volatile unsigned short *dmawp
;
282 unsigned short count
;
285 printk("get_dma_residue(dmanr=%d)\n", dmanr
);
288 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
289 count
= dmawp
[MCFDMA_BCR
];
292 #else /* CONFIG_M5272 is defined */
295 * The MCF5272 DMA controller is very different than the controller defined above
296 * in terms of register mapping. For instance, with the exception of the 16-bit
297 * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
299 * The big difference, however, is the lack of device-requested DMA. All modes
300 * are dual address transfer, and there is no 'device' setup or direction bit.
301 * You can DMA between a device and memory, between memory and memory, or even between
302 * two devices directly, with any combination of incrementing and non-incrementing
303 * addresses you choose. This puts a crimp in distinguishing between the 'device
304 * address' set up by set_dma_device_addr.
306 * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
307 * which will act exactly as above in -- it will look to see if the source is set to
308 * autoincrement, and if so it will make the source use the set_dma_addr value and the
309 * destination the set_dma_device_addr value. Otherwise the source will be set to the
310 * set_dma_device_addr value and the destination will get the set_dma_addr value.
312 * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
313 * and make it explicit. Depending on what you're doing, one of these two should work
314 * for you, but don't mix them in the same transfer setup.
317 /* enable/disable a specific DMA channel */
318 static __inline__
void enable_dma(unsigned int dmanr
)
320 volatile unsigned int *dmalp
;
323 printk("enable_dma(dmanr=%d)\n", dmanr
);
326 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
327 dmalp
[MCFDMA_DMR
] |= MCFDMA_DMR_EN
;
330 static __inline__
void disable_dma(unsigned int dmanr
)
332 volatile unsigned int *dmalp
;
335 printk("disable_dma(dmanr=%d)\n", dmanr
);
338 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
340 /* Turn off external requests, and stop any DMA in progress */
341 dmalp
[MCFDMA_DMR
] &= ~MCFDMA_DMR_EN
;
342 dmalp
[MCFDMA_DMR
] |= MCFDMA_DMR_RESET
;
346 * Clear the 'DMA Pointer Flip Flop'.
347 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
348 * Use this once to initialize the FF to a known state.
349 * After that, keep track of it. :-)
350 * --- In order to do that, the DMA routines below should ---
351 * --- only be used while interrupts are disabled! ---
353 * This is a NOP for ColdFire. Provide a stub for compatibility.
355 static __inline__
void clear_dma_ff(unsigned int dmanr
)
359 /* set mode (above) for a specific DMA channel */
360 static __inline__
void set_dma_mode(unsigned int dmanr
, char mode
)
363 volatile unsigned int *dmalp
;
364 volatile unsigned short *dmawp
;
367 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr
, mode
);
369 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
370 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
372 // Clear config errors
373 dmalp
[MCFDMA_DMR
] |= MCFDMA_DMR_RESET
;
375 // Set command register
377 MCFDMA_DMR_RQM_DUAL
| // Mandatory Request Mode setting
378 MCFDMA_DMR_DSTT_SD
| // Set up addressing types; set to supervisor-data.
379 MCFDMA_DMR_SRCT_SD
| // Set up addressing types; set to supervisor-data.
380 // source static-address-mode
381 ((mode
& DMA_MODE_SRC_SA_BIT
) ? MCFDMA_DMR_SRCM_SA
: MCFDMA_DMR_SRCM_IA
) |
382 // dest static-address-mode
383 ((mode
& DMA_MODE_DES_SA_BIT
) ? MCFDMA_DMR_DSTM_SA
: MCFDMA_DMR_DSTM_IA
) |
384 // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272
385 (((mode
& DMA_MODE_SSIZE_MASK
) >> DMA_MODE_SSIZE_OFF
) << MCFDMA_DMR_DSTS_OFF
) |
386 (((mode
& DMA_MODE_SSIZE_MASK
) >> DMA_MODE_SSIZE_OFF
) << MCFDMA_DMR_SRCS_OFF
);
388 dmawp
[MCFDMA_DIR
] |= MCFDMA_DIR_ASCEN
; /* Enable completion interrupts */
391 printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__
, __LINE__
,
392 dmanr
, (int) &dmalp
[MCFDMA_DMR
], dmabp
[MCFDMA_DMR
],
393 (int) &dmawp
[MCFDMA_DIR
], dmawp
[MCFDMA_DIR
]);
397 /* Set transfer address for specific DMA channel */
398 static __inline__
void set_dma_addr(unsigned int dmanr
, unsigned int a
)
400 volatile unsigned int *dmalp
;
403 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
406 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
408 // Determine which address registers are used for memory/device accesses
409 if (dmalp
[MCFDMA_DMR
] & MCFDMA_DMR_SRCM
) {
410 // Source incrementing, must be memory
411 dmalp
[MCFDMA_DSAR
] = a
;
412 // Set dest address, must be device
413 dmalp
[MCFDMA_DDAR
] = dma_device_address
[dmanr
];
415 // Destination incrementing, must be memory
416 dmalp
[MCFDMA_DDAR
] = a
;
417 // Set source address, must be device
418 dmalp
[MCFDMA_DSAR
] = dma_device_address
[dmanr
];
422 printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
423 __FILE__
, __LINE__
, dmanr
, (int) &dmawp
[MCFDMA_DMR
], dmawp
[MCFDMA_DMR
],
424 (int) &dmalp
[MCFDMA_DSAR
], dmalp
[MCFDMA_DSAR
],
425 (int) &dmalp
[MCFDMA_DDAR
], dmalp
[MCFDMA_DDAR
]);
430 * Specific for Coldfire - sets device address.
431 * Should be called after the mode set call, and before set DMA address.
433 static __inline__
void set_dma_device_addr(unsigned int dmanr
, unsigned int a
)
436 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
439 dma_device_address
[dmanr
] = a
;
443 * NOTE 2: "count" represents _bytes_.
445 * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
447 static __inline__
void set_dma_count(unsigned int dmanr
, unsigned int count
)
449 volatile unsigned int *dmalp
;
452 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr
, count
);
455 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
456 dmalp
[MCFDMA_DBCR
] = count
;
460 * Get DMA residue count. After a DMA transfer, this
461 * should return zero. Reading this while a DMA transfer is
462 * still in progress will return unpredictable results.
463 * Otherwise, it returns the number of _bytes_ left to transfer.
465 static __inline__
int get_dma_residue(unsigned int dmanr
)
467 volatile unsigned int *dmalp
;
471 printk("get_dma_residue(dmanr=%d)\n", dmanr
);
474 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
475 count
= dmalp
[MCFDMA_DBCR
];
479 #endif /* !defined(CONFIG_M5272) */
480 #endif /* CONFIG_COLDFIRE */
482 #define MAX_DMA_CHANNELS 8
484 /* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
485 occurrence should be flagged as an error. */
486 /* under 2.4 it is actually needed by the new bootmem allocator */
487 #define MAX_DMA_ADDRESS PAGE_OFFSET
489 /* These are in kernel/dma.c: */
490 extern int request_dma(unsigned int dmanr
, const char *device_id
); /* reserve a DMA channel */
491 extern void free_dma(unsigned int dmanr
); /* release it again */
493 #endif /* _M68K_DMA_H */