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git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - include/asm-m68knommu/dma.h
6 #include <linux/config.h>
11 * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
12 * address mode emits a source address, and expects that the device will either
13 * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
14 * the device will place data on the correct byte(s) of the data bus, as the
15 * memory transactions are always 32 bits. This implies that only 32 bit
16 * devices will find single mode transfers useful. Dual address DMA mode
17 * performs two cycles: source read and destination write. ColdFire will
18 * align the data so that the device will always get the correct bytes, thus
19 * is useful for 8 and 16 bit devices. This is the mode that is supported
22 * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
23 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
25 * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
26 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
28 * APR/18/2002 : added proper support for MCF5272 DMA controller.
29 * Arthur Shipkowski (art@videon-central.com)
32 #include <asm/coldfire.h>
33 #include <asm/mcfsim.h>
34 #include <asm/mcfdma.h>
37 * Set number of channels of DMA on ColdFire for different implementations.
39 #if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
40 #define MAX_M68K_DMA_CHANNELS 4
41 #elif defined(CONFIG_M5272)
42 #define MAX_M68K_DMA_CHANNELS 1
44 #define MAX_M68K_DMA_CHANNELS 2
47 extern unsigned int dma_base_addr
[MAX_M68K_DMA_CHANNELS
];
48 extern unsigned int dma_device_address
[MAX_M68K_DMA_CHANNELS
];
50 #if !defined(CONFIG_M5272)
51 #define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
52 #define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
53 #define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
54 #define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
56 /* I/O to memory, 8 bits, mode */
57 #define DMA_MODE_READ 0
58 /* memory to I/O, 8 bits, mode */
59 #define DMA_MODE_WRITE 1
60 /* I/O to memory, 16 bits, mode */
61 #define DMA_MODE_READ_WORD 2
62 /* memory to I/O, 16 bits, mode */
63 #define DMA_MODE_WRITE_WORD 3
64 /* I/O to memory, 32 bits, mode */
65 #define DMA_MODE_READ_LONG 4
66 /* memory to I/O, 32 bits, mode */
67 #define DMA_MODE_WRITE_LONG 5
68 /* I/O to memory, 8 bits, single-address-mode */
69 #define DMA_MODE_READ_SINGLE 8
70 /* memory to I/O, 8 bits, single-address-mode */
71 #define DMA_MODE_WRITE_SINGLE 9
72 /* I/O to memory, 16 bits, single-address-mode */
73 #define DMA_MODE_READ_WORD_SINGLE 10
74 /* memory to I/O, 16 bits, single-address-mode */
75 #define DMA_MODE_WRITE_WORD_SINGLE 11
76 /* I/O to memory, 32 bits, single-address-mode */
77 #define DMA_MODE_READ_LONG_SINGLE 12
78 /* memory to I/O, 32 bits, single-address-mode */
79 #define DMA_MODE_WRITE_LONG_SINGLE 13
81 #else /* CONFIG_M5272 is defined */
83 /* Source static-address mode */
84 #define DMA_MODE_SRC_SA_BIT 0x01
85 /* Two bits to select between all four modes */
86 #define DMA_MODE_SSIZE_MASK 0x06
87 /* Offset to shift bits in */
88 #define DMA_MODE_SSIZE_OFF 0x01
89 /* Destination static-address mode */
90 #define DMA_MODE_DES_SA_BIT 0x10
91 /* Two bits to select between all four modes */
92 #define DMA_MODE_DSIZE_MASK 0x60
93 /* Offset to shift bits in */
94 #define DMA_MODE_DSIZE_OFF 0x05
96 #define DMA_MODE_SIZE_LONG 0x00
97 #define DMA_MODE_SIZE_BYTE 0x01
98 #define DMA_MODE_SIZE_WORD 0x02
99 #define DMA_MODE_SIZE_LINE 0x03
102 * Aliases to help speed quick ports; these may be suboptimal, however. They
103 * do not include the SINGLE mode modifiers since the MCF5272 does not have a
104 * mode where the device is in control of its addressing.
107 /* I/O to memory, 8 bits, mode */
108 #define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
109 /* memory to I/O, 8 bits, mode */
110 #define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
111 /* I/O to memory, 16 bits, mode */
112 #define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
113 /* memory to I/O, 16 bits, mode */
114 #define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
115 /* I/O to memory, 32 bits, mode */
116 #define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
117 /* memory to I/O, 32 bits, mode */
118 #define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
120 #endif /* !defined(CONFIG_M5272) */
122 #if !defined(CONFIG_M5272)
123 /* enable/disable a specific DMA channel */
124 static __inline__
void enable_dma(unsigned int dmanr
)
126 volatile unsigned short *dmawp
;
129 printk("enable_dma(dmanr=%d)\n", dmanr
);
132 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
133 dmawp
[MCFDMA_DCR
] |= MCFDMA_DCR_EEXT
;
136 static __inline__
void disable_dma(unsigned int dmanr
)
138 volatile unsigned short *dmawp
;
139 volatile unsigned char *dmapb
;
142 printk("disable_dma(dmanr=%d)\n", dmanr
);
145 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
146 dmapb
= (unsigned char *) dma_base_addr
[dmanr
];
148 /* Turn off external requests, and stop any DMA in progress */
149 dmawp
[MCFDMA_DCR
] &= ~MCFDMA_DCR_EEXT
;
150 dmapb
[MCFDMA_DSR
] = MCFDMA_DSR_DONE
;
154 * Clear the 'DMA Pointer Flip Flop'.
155 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
156 * Use this once to initialize the FF to a known state.
157 * After that, keep track of it. :-)
158 * --- In order to do that, the DMA routines below should ---
159 * --- only be used while interrupts are disabled! ---
161 * This is a NOP for ColdFire. Provide a stub for compatibility.
163 static __inline__
void clear_dma_ff(unsigned int dmanr
)
167 /* set mode (above) for a specific DMA channel */
168 static __inline__
void set_dma_mode(unsigned int dmanr
, char mode
)
171 volatile unsigned char *dmabp
;
172 volatile unsigned short *dmawp
;
175 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr
, mode
);
178 dmabp
= (unsigned char *) dma_base_addr
[dmanr
];
179 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
181 // Clear config errors
182 dmabp
[MCFDMA_DSR
] = MCFDMA_DSR_DONE
;
184 // Set command register
186 MCFDMA_DCR_INT
| // Enable completion irq
187 MCFDMA_DCR_CS
| // Force one xfer per request
188 MCFDMA_DCR_AA
| // Enable auto alignment
189 // single-address-mode
190 ((mode
& DMA_MODE_SINGLE_BIT
) ? MCFDMA_DCR_SAA
: 0) |
191 // sets s_rw (-> r/w) high if Memory to I/0
192 ((mode
& DMA_MODE_WRITE_BIT
) ? MCFDMA_DCR_S_RW
: 0) |
193 // Memory to I/O or I/O to Memory
194 ((mode
& DMA_MODE_WRITE_BIT
) ? MCFDMA_DCR_SINC
: MCFDMA_DCR_DINC
) |
195 // 32 bit, 16 bit or 8 bit transfers
196 ((mode
& DMA_MODE_WORD_BIT
) ? MCFDMA_DCR_SSIZE_WORD
:
197 ((mode
& DMA_MODE_LONG_BIT
) ? MCFDMA_DCR_SSIZE_LONG
:
198 MCFDMA_DCR_SSIZE_BYTE
)) |
199 ((mode
& DMA_MODE_WORD_BIT
) ? MCFDMA_DCR_DSIZE_WORD
:
200 ((mode
& DMA_MODE_LONG_BIT
) ? MCFDMA_DCR_DSIZE_LONG
:
201 MCFDMA_DCR_DSIZE_BYTE
));
204 printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__
, __LINE__
,
205 dmanr
, (int) &dmabp
[MCFDMA_DSR
], dmabp
[MCFDMA_DSR
],
206 (int) &dmawp
[MCFDMA_DCR
], dmawp
[MCFDMA_DCR
]);
210 /* Set transfer address for specific DMA channel */
211 static __inline__
void set_dma_addr(unsigned int dmanr
, unsigned int a
)
213 volatile unsigned short *dmawp
;
214 volatile unsigned int *dmalp
;
217 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
220 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
221 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
223 // Determine which address registers are used for memory/device accesses
224 if (dmawp
[MCFDMA_DCR
] & MCFDMA_DCR_SINC
) {
225 // Source incrementing, must be memory
226 dmalp
[MCFDMA_SAR
] = a
;
227 // Set dest address, must be device
228 dmalp
[MCFDMA_DAR
] = dma_device_address
[dmanr
];
230 // Destination incrementing, must be memory
231 dmalp
[MCFDMA_DAR
] = a
;
232 // Set source address, must be device
233 dmalp
[MCFDMA_SAR
] = dma_device_address
[dmanr
];
237 printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
238 __FILE__
, __LINE__
, dmanr
, (int) &dmawp
[MCFDMA_DCR
], dmawp
[MCFDMA_DCR
],
239 (int) &dmalp
[MCFDMA_SAR
], dmalp
[MCFDMA_SAR
],
240 (int) &dmalp
[MCFDMA_DAR
], dmalp
[MCFDMA_DAR
]);
245 * Specific for Coldfire - sets device address.
246 * Should be called after the mode set call, and before set DMA address.
248 static __inline__
void set_dma_device_addr(unsigned int dmanr
, unsigned int a
)
251 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
254 dma_device_address
[dmanr
] = a
;
258 * NOTE 2: "count" represents _bytes_.
260 static __inline__
void set_dma_count(unsigned int dmanr
, unsigned int count
)
262 volatile unsigned short *dmawp
;
265 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr
, count
);
268 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
269 dmawp
[MCFDMA_BCR
] = (unsigned short)count
;
273 * Get DMA residue count. After a DMA transfer, this
274 * should return zero. Reading this while a DMA transfer is
275 * still in progress will return unpredictable results.
276 * Otherwise, it returns the number of _bytes_ left to transfer.
278 static __inline__
int get_dma_residue(unsigned int dmanr
)
280 volatile unsigned short *dmawp
;
281 unsigned short count
;
284 printk("get_dma_residue(dmanr=%d)\n", dmanr
);
287 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
288 count
= dmawp
[MCFDMA_BCR
];
291 #else /* CONFIG_M5272 is defined */
294 * The MCF5272 DMA controller is very different than the controller defined above
295 * in terms of register mapping. For instance, with the exception of the 16-bit
296 * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
298 * The big difference, however, is the lack of device-requested DMA. All modes
299 * are dual address transfer, and there is no 'device' setup or direction bit.
300 * You can DMA between a device and memory, between memory and memory, or even between
301 * two devices directly, with any combination of incrementing and non-incrementing
302 * addresses you choose. This puts a crimp in distinguishing between the 'device
303 * address' set up by set_dma_device_addr.
305 * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
306 * which will act exactly as above in -- it will look to see if the source is set to
307 * autoincrement, and if so it will make the source use the set_dma_addr value and the
308 * destination the set_dma_device_addr value. Otherwise the source will be set to the
309 * set_dma_device_addr value and the destination will get the set_dma_addr value.
311 * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
312 * and make it explicit. Depending on what you're doing, one of these two should work
313 * for you, but don't mix them in the same transfer setup.
316 /* enable/disable a specific DMA channel */
317 static __inline__
void enable_dma(unsigned int dmanr
)
319 volatile unsigned int *dmalp
;
322 printk("enable_dma(dmanr=%d)\n", dmanr
);
325 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
326 dmalp
[MCFDMA_DMR
] |= MCFDMA_DMR_EN
;
329 static __inline__
void disable_dma(unsigned int dmanr
)
331 volatile unsigned int *dmalp
;
334 printk("disable_dma(dmanr=%d)\n", dmanr
);
337 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
339 /* Turn off external requests, and stop any DMA in progress */
340 dmalp
[MCFDMA_DMR
] &= ~MCFDMA_DMR_EN
;
341 dmalp
[MCFDMA_DMR
] |= MCFDMA_DMR_RESET
;
345 * Clear the 'DMA Pointer Flip Flop'.
346 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
347 * Use this once to initialize the FF to a known state.
348 * After that, keep track of it. :-)
349 * --- In order to do that, the DMA routines below should ---
350 * --- only be used while interrupts are disabled! ---
352 * This is a NOP for ColdFire. Provide a stub for compatibility.
354 static __inline__
void clear_dma_ff(unsigned int dmanr
)
358 /* set mode (above) for a specific DMA channel */
359 static __inline__
void set_dma_mode(unsigned int dmanr
, char mode
)
362 volatile unsigned int *dmalp
;
363 volatile unsigned short *dmawp
;
366 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr
, mode
);
368 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
369 dmawp
= (unsigned short *) dma_base_addr
[dmanr
];
371 // Clear config errors
372 dmalp
[MCFDMA_DMR
] |= MCFDMA_DMR_RESET
;
374 // Set command register
376 MCFDMA_DMR_RQM_DUAL
| // Mandatory Request Mode setting
377 MCFDMA_DMR_DSTT_SD
| // Set up addressing types; set to supervisor-data.
378 MCFDMA_DMR_SRCT_SD
| // Set up addressing types; set to supervisor-data.
379 // source static-address-mode
380 ((mode
& DMA_MODE_SRC_SA_BIT
) ? MCFDMA_DMR_SRCM_SA
: MCFDMA_DMR_SRCM_IA
) |
381 // dest static-address-mode
382 ((mode
& DMA_MODE_DES_SA_BIT
) ? MCFDMA_DMR_DSTM_SA
: MCFDMA_DMR_DSTM_IA
) |
383 // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272
384 (((mode
& DMA_MODE_SSIZE_MASK
) >> DMA_MODE_SSIZE_OFF
) << MCFDMA_DMR_DSTS_OFF
) |
385 (((mode
& DMA_MODE_SSIZE_MASK
) >> DMA_MODE_SSIZE_OFF
) << MCFDMA_DMR_SRCS_OFF
);
387 dmawp
[MCFDMA_DIR
] |= MCFDMA_DIR_ASCEN
; /* Enable completion interrupts */
390 printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__
, __LINE__
,
391 dmanr
, (int) &dmalp
[MCFDMA_DMR
], dmabp
[MCFDMA_DMR
],
392 (int) &dmawp
[MCFDMA_DIR
], dmawp
[MCFDMA_DIR
]);
396 /* Set transfer address for specific DMA channel */
397 static __inline__
void set_dma_addr(unsigned int dmanr
, unsigned int a
)
399 volatile unsigned int *dmalp
;
402 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
405 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
407 // Determine which address registers are used for memory/device accesses
408 if (dmalp
[MCFDMA_DMR
] & MCFDMA_DMR_SRCM
) {
409 // Source incrementing, must be memory
410 dmalp
[MCFDMA_DSAR
] = a
;
411 // Set dest address, must be device
412 dmalp
[MCFDMA_DDAR
] = dma_device_address
[dmanr
];
414 // Destination incrementing, must be memory
415 dmalp
[MCFDMA_DDAR
] = a
;
416 // Set source address, must be device
417 dmalp
[MCFDMA_DSAR
] = dma_device_address
[dmanr
];
421 printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
422 __FILE__
, __LINE__
, dmanr
, (int) &dmawp
[MCFDMA_DMR
], dmawp
[MCFDMA_DMR
],
423 (int) &dmalp
[MCFDMA_DSAR
], dmalp
[MCFDMA_DSAR
],
424 (int) &dmalp
[MCFDMA_DDAR
], dmalp
[MCFDMA_DDAR
]);
429 * Specific for Coldfire - sets device address.
430 * Should be called after the mode set call, and before set DMA address.
432 static __inline__
void set_dma_device_addr(unsigned int dmanr
, unsigned int a
)
435 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr
, a
);
438 dma_device_address
[dmanr
] = a
;
442 * NOTE 2: "count" represents _bytes_.
444 * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
446 static __inline__
void set_dma_count(unsigned int dmanr
, unsigned int count
)
448 volatile unsigned int *dmalp
;
451 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr
, count
);
454 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
455 dmalp
[MCFDMA_DBCR
] = count
;
459 * Get DMA residue count. After a DMA transfer, this
460 * should return zero. Reading this while a DMA transfer is
461 * still in progress will return unpredictable results.
462 * Otherwise, it returns the number of _bytes_ left to transfer.
464 static __inline__
int get_dma_residue(unsigned int dmanr
)
466 volatile unsigned int *dmalp
;
470 printk("get_dma_residue(dmanr=%d)\n", dmanr
);
473 dmalp
= (unsigned int *) dma_base_addr
[dmanr
];
474 count
= dmalp
[MCFDMA_DBCR
];
478 #endif /* !defined(CONFIG_M5272) */
479 #endif /* CONFIG_COLDFIRE */
481 #define MAX_DMA_CHANNELS 8
483 /* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
484 occurrence should be flagged as an error. */
485 /* under 2.4 it is actually needed by the new bootmem allocator */
486 #define MAX_DMA_ADDRESS PAGE_OFFSET
488 /* These are in kernel/dma.c: */
489 extern int request_dma(unsigned int dmanr
, const char *device_id
); /* reserve a DMA channel */
490 extern void free_dma(unsigned int dmanr
); /* release it again */
492 #endif /* _M68K_DMA_H */