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git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - include/asm-m68knommu/mcfuart.h
1 /****************************************************************************/
4 * mcfuart.h -- ColdFire internal UART support defines.
6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
10 /****************************************************************************/
13 /****************************************************************************/
15 #include <linux/config.h>
18 * Define the base address of the UARTS within the MBAR address
21 #if defined(CONFIG_M5272)
22 #define MCFUART_BASE1 0x100 /* Base address of UART1 */
23 #define MCFUART_BASE2 0x140 /* Base address of UART2 */
24 #elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
25 #if defined(CONFIG_NETtel)
26 #define MCFUART_BASE1 0x180 /* Base address of UART1 */
27 #define MCFUART_BASE2 0x140 /* Base address of UART2 */
29 #define MCFUART_BASE1 0x140 /* Base address of UART1 */
30 #define MCFUART_BASE2 0x180 /* Base address of UART2 */
32 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
33 #define MCFUART_BASE1 0x200 /* Base address of UART1 */
34 #define MCFUART_BASE2 0x240 /* Base address of UART2 */
35 #define MCFUART_BASE3 0x280 /* Base address of UART3 */
36 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
37 #if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
38 #define MCFUART_BASE1 0x200 /* Base address of UART1 */
39 #define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
41 #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
42 #define MCFUART_BASE2 0x200 /* Base address of UART2 */
44 #elif defined(CONFIG_M520x)
45 #define MCFUART_BASE1 0x60000 /* Base address of UART1 */
46 #define MCFUART_BASE2 0x64000 /* Base address of UART2 */
47 #define MCFUART_BASE3 0x68000 /* Base address of UART2 */
52 * Define the ColdFire UART register set addresses.
54 #define MCFUART_UMR 0x00 /* Mode register (r/w) */
55 #define MCFUART_USR 0x04 /* Status register (r) */
56 #define MCFUART_UCSR 0x04 /* Clock Select (w) */
57 #define MCFUART_UCR 0x08 /* Command register (w) */
58 #define MCFUART_URB 0x0c /* Receiver Buffer (r) */
59 #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
60 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
61 #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
62 #define MCFUART_UISR 0x14 /* Interrup Status (r) */
63 #define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
64 #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
65 #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
67 #define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
68 #define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
69 #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
71 #define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
73 #define MCFUART_UIPR 0x34 /* Input Port (r) */
74 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
75 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
79 * Define bit flags in Mode Register 1 (MR1).
81 #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
82 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
83 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
84 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
85 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
87 #define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
88 #define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
89 #define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
90 #define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
91 #define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
93 #define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
94 #define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
95 #define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
96 #define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
99 * Define bit flags in Mode Register 2 (MR2).
101 #define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
102 #define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
103 #define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
104 #define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
105 #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
107 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
108 #define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
109 #define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
112 * Define bit flags in Status Register (USR).
114 #define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
115 #define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
116 #define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
117 #define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
118 #define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
119 #define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
120 #define MCFUART_USR_RXFULL 0x02 /* Receiver full */
121 #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
123 #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
124 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
127 * Define bit flags in Clock Select Register (UCSR).
129 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
130 #define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
131 #define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
133 #define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
134 #define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
135 #define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
138 * Define bit flags in Command Register (UCR).
140 #define MCFUART_UCR_CMDNULL 0x00 /* No command */
141 #define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
142 #define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
143 #define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
144 #define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
145 #define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
146 #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
147 #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
149 #define MCFUART_UCR_TXNULL 0x00 /* No TX command */
150 #define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
151 #define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
152 #define MCFUART_UCR_RXNULL 0x00 /* No RX command */
153 #define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
154 #define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
157 * Define bit flags in Input Port Change Register (UIPCR).
159 #define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
160 #define MCFUART_UIPCR_CTS 0x01 /* CTS value */
163 * Define bit flags in Input Port Register (UIP).
165 #define MCFUART_UIPR_CTS 0x01 /* CTS value */
168 * Define bit flags in Output Port Registers (UOP).
169 * Clear bit by writing to UOP0, set by writing to UOP1.
171 #define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
174 * Define bit flags in the Auxiliary Control Register (UACR).
176 #define MCFUART_UACR_IEC 0x01 /* Input enable control */
179 * Define bit flags in Interrupt Status Register (UISR).
180 * These same bits are used for the Interrupt Mask Register (UIMR).
182 #define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
183 #define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
184 #define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
185 #define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
189 * Define bit flags in the Transmitter FIFO Register (UTF).
191 #define MCFUART_UTF_TXB 0x1f /* Transmitter data level */
192 #define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */
193 #define MCFUART_UTF_TXS 0xc0 /* Transmitter status */
196 * Define bit flags in the Receiver FIFO Register (URF).
198 #define MCFUART_URF_RXB 0x1f /* Receiver data level */
199 #define MCFUART_URF_FULL 0x20 /* Receiver fifo full */
200 #define MCFUART_URF_RXS 0xc0 /* Receiver status */
203 /****************************************************************************/
204 #endif /* mcfuart_h */