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2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 * Some useful macros for MIPS assembler code
13 * Some of the routines below contain useless nops that will be optimized
14 * away by gas in -O mode. These nops are however required to fill delay
15 * slots in noreorder mode.
20 #include <linux/config.h>
21 #include <asm/sgidefs.h>
25 #define __CAT(str1,str2) str1##str2
27 #define __CAT(str1,str2) str1/**/str2
29 #define CAT(str1,str2) __CAT(str1,str2)
33 * PIC specific declarations
34 * Not used for the kernel but here seems to be the right place.
37 #define CPRESTORE(register) \
39 #define CPADD(register) \
41 #define CPLOAD(register) \
44 #define CPRESTORE(register)
45 #define CPADD(register)
46 #define CPLOAD(register)
50 * LEAF - declare leaf routine
52 #define LEAF(symbol) \
55 .type symbol,@function; \
57 symbol: .frame sp,0,ra
60 * NESTED - declare nested routine entry point
62 #define NESTED(symbol, framesize, rpc) \
65 .type symbol,@function; \
67 symbol: .frame sp, framesize, rpc
70 * END - mark end of function
72 #define END(function) \
74 .size function,.-function
77 * EXPORT - export definition of symbol
79 #define EXPORT(symbol) \
84 * FEXPORT - export definition of a function symbol
86 #define FEXPORT(symbol) \
88 .type symbol,@function; \
92 * ABS - export absolute symbol
94 #define ABS(symbol,value) \
108 * Print formatted string
111 #define PRINT(string) \
119 #define PRINT(string)
123 .pushsection .data; \
130 #define TTABLE(string) \
131 .pushsection .text; \
134 .pushsection .data; \
139 * MIPS IV pref instruction.
140 * Use with .set noreorder only!
142 * MIPS IV implementations are free to treat this as a nop. The R5000
143 * is one of them. So we should have an option not to use this instruction.
145 #ifdef CONFIG_CPU_HAS_PREFETCH
147 #define PREF(hint,addr) \
153 #define PREFX(hint,addr) \
159 #else /* !CONFIG_CPU_HAS_PREFETCH */
161 #define PREF(hint,addr)
162 #define PREFX(hint,addr)
164 #endif /* !CONFIG_CPU_HAS_PREFETCH */
167 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
169 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
170 #define MOVN(rd,rs,rt) \
177 #define MOVZ(rd,rs,rt) \
184 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
185 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
186 #define MOVN(rd,rs,rt) \
193 #define MOVZ(rd,rs,rt) \
200 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
201 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
202 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
203 #define MOVN(rd,rs,rt) \
205 #define MOVZ(rd,rs,rt) \
207 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
212 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
216 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
222 * Macros to handle different pointer/register sizes for 32/64-bit code
235 * Use the following macros in assemblercode to load/store registers,
238 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
241 #define REG_SUBU subu
242 #define REG_ADDU addu
244 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
247 #define REG_SUBU dsubu
248 #define REG_ADDU daddu
252 * How to add/sub/load/store/shift C int variables.
254 #if (_MIPS_SZINT == 32)
256 #define INT_ADDU addu
257 #define INT_ADDI addi
258 #define INT_ADDIU addiu
260 #define INT_SUBU subu
264 #define INT_SLLV sllv
266 #define INT_SRLV srlv
268 #define INT_SRAV srav
271 #if (_MIPS_SZINT == 64)
273 #define INT_ADDU daddu
274 #define INT_ADDI daddi
275 #define INT_ADDIU daddiu
277 #define INT_SUBU dsubu
281 #define INT_SLLV dsllv
283 #define INT_SRLV dsrlv
285 #define INT_SRAV dsrav
289 * How to add/sub/load/store/shift C long variables.
291 #if (_MIPS_SZLONG == 32)
293 #define LONG_ADDU addu
294 #define LONG_ADDI addi
295 #define LONG_ADDIU addiu
297 #define LONG_SUBU subu
301 #define LONG_SLLV sllv
303 #define LONG_SRLV srlv
305 #define LONG_SRAV srav
313 #if (_MIPS_SZLONG == 64)
314 #define LONG_ADD dadd
315 #define LONG_ADDU daddu
316 #define LONG_ADDI daddi
317 #define LONG_ADDIU daddiu
318 #define LONG_SUB dsub
319 #define LONG_SUBU dsubu
322 #define LONG_SLL dsll
323 #define LONG_SLLV dsllv
324 #define LONG_SRL dsrl
325 #define LONG_SRLV dsrlv
326 #define LONG_SRA dsra
327 #define LONG_SRAV dsrav
336 * How to add/sub/load/store/shift pointers.
338 #if (_MIPS_SZPTR == 32)
340 #define PTR_ADDU addu
341 #define PTR_ADDI addi
342 #define PTR_ADDIU addiu
344 #define PTR_SUBU subu
349 #define PTR_SLLV sllv
351 #define PTR_SRLV srlv
353 #define PTR_SRAV srav
355 #define PTR_SCALESHIFT 2
362 #if (_MIPS_SZPTR == 64)
364 #define PTR_ADDU daddu
365 #define PTR_ADDI daddi
366 #define PTR_ADDIU daddiu
368 #define PTR_SUBU dsubu
373 #define PTR_SLLV dsllv
375 #define PTR_SRLV dsrlv
377 #define PTR_SRAV dsrav
379 #define PTR_SCALESHIFT 3
387 * Some cp0 registers were extended to 64bit for MIPS III.
389 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
393 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
398 #define SSNOP sll zero,zero,1
400 #endif /* __ASM_ASM_H */