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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - include/asm-mips/hazards.h
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #ifndef _ASM_HAZARDS_H
11 #define _ASM_HAZARDS_H
13 #include <linux/config.h>
26 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
27 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
28 * for data translations should not occur for 3 cpu cycles.
30 #ifdef CONFIG_CPU_RM9000
32 .macro mtc0_tlbw_hazard
35 _ssnop
; _ssnop
; _ssnop
; _ssnop
39 .macro tlbw_eret_hazard
42 _ssnop
; _ssnop
; _ssnop
; _ssnop
49 * The taken branch will result in a two cycle penalty for the two killed
50 * instructions on R4000 / R4400. Other processors only have a single cycle
51 * hazard so this is nice trick to have an optimal code for a range of
54 .macro mtc0_tlbw_hazard
58 .macro tlbw_eret_hazard
64 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
65 * It is a MIPS32R2 processor so ehb will clear the hazard.
68 #ifdef CONFIG_CPU_MIPSR2
70 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
73 #define irq_enable_hazard
76 #define irq_disable_hazard
79 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
82 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
85 #define irq_enable_hazard
87 #define irq_disable_hazard
92 * Classic MIPS needs 1 - 3 nops or ssnops
94 #define irq_enable_hazard
95 #define irq_disable_hazard \
96 _ssnop; _ssnop; _ssnop
100 #else /* __ASSEMBLY__ */
111 #ifdef CONFIG_CPU_RM9000
114 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
115 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
116 * for data translations should not occur for 3 cpu cycles.
119 #define mtc0_tlbw_hazard() \
120 __asm__ __volatile__( \
128 #define tlbw_use_hazard() \
129 __asm__ __volatile__( \
140 * Overkill warning ...
142 #define mtc0_tlbw_hazard() \
143 __asm__ __volatile__( \
144 " .set noreorder \n" \
153 #define tlbw_use_hazard() \
154 __asm__ __volatile__( \
155 " .set noreorder \n" \
167 * Interrupt enable/disable hazards
168 * Some processors have hazards when modifying
169 * the status register to change the interrupt state
172 #ifdef CONFIG_CPU_MIPSR2
174 __asm__(" .macro irq_enable_hazard \n"
178 " .macro irq_disable_hazard \n"
182 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
185 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
189 " .macro irq_enable_hazard \n"
192 " .macro irq_disable_hazard \n"
198 * Default for classic MIPS processors. Assume worst case hazards but don't
199 * care about the irq_enable_hazard - sooner or later the hardware will
200 * enable it and we don't care when exactly.
205 " # There is a hazard but we do not care \n"
207 " .macro\tirq_enable_hazard \n"
210 " .macro\tirq_disable_hazard \n"
218 #define irq_enable_hazard() \
219 __asm__ __volatile__("irq_enable_hazard")
220 #define irq_disable_hazard() \
221 __asm__ __volatile__("irq_disable_hazard")
225 * Back-to-back hazards -
227 * What is needed to separate a move to cp0 from a subsequent read from the
230 #ifdef CONFIG_CPU_MIPSR2
232 __asm__(" .macro back_to_back_c0_hazard \n"
236 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
237 defined(CONFIG_CPU_SB1)
239 __asm__(" .macro back_to_back_c0_hazard \n"
244 __asm__(" .macro back_to_back_c0_hazard \n"
254 #define back_to_back_c0_hazard() \
255 __asm__ __volatile__("back_to_back_c0_hazard")
259 * Instruction execution hazard
261 #ifdef CONFIG_CPU_MIPSR2
263 * gcc has a tradition of misscompiling the previous construct using the
264 * address of a label as argument to inline assembler. Gas otoh has the
265 * annoying difference between la and dla which are only usable for 32-bit
266 * rsp. 64-bit code, so can't be used without conditional compilation.
267 * The alterantive is switching the assembler to 64-bit code which happens
268 * to work right even for 32-bit code ...
270 #define instruction_hazard() \
274 __asm__ __volatile__( \
275 " .set mips64r2 \n" \
284 #define instruction_hazard() do { } while (0)
287 #endif /* __ASSEMBLY__ */
289 #endif /* _ASM_HAZARDS_H */