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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - include/asm-mips/hazards.h
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
11 #include <linux/config.h>
24 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
25 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
26 * for data translations should not occur for 3 cpu cycles.
28 #ifdef CONFIG_CPU_RM9000
30 .macro mtc0_tlbw_hazard
33 _ssnop
; _ssnop
; _ssnop
; _ssnop
37 .macro tlbw_eret_hazard
40 _ssnop
; _ssnop
; _ssnop
; _ssnop
47 * The taken branch will result in a two cycle penalty for the two killed
48 * instructions on R4000 / R4400. Other processors only have a single cycle
49 * hazard so this is nice trick to have an optimal code for a range of
52 .macro mtc0_tlbw_hazard
56 .macro tlbw_eret_hazard
62 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
63 * It is a MIPS32R2 processor so ehb will clear the hazard.
66 #ifdef CONFIG_CPU_MIPSR2
68 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
71 #define irq_enable_hazard
74 #define irq_disable_hazard
77 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
78 defined(CONFIG_CPU_SB1)
81 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
84 #define irq_enable_hazard
86 #define irq_disable_hazard
91 * Classic MIPS needs 1 - 3 nops or ssnops
93 #define irq_enable_hazard
94 #define irq_disable_hazard \
95 _ssnop; _ssnop; _ssnop
99 #else /* __ASSEMBLY__ */
102 " .macro _ssnop \n\t"
103 " sll $0, $0, 1 \n\t"
107 " sll $0, $0, 3 \n\t"
110 #ifdef CONFIG_CPU_RM9000
113 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
114 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
115 * for data translations should not occur for 3 cpu cycles.
118 #define mtc0_tlbw_hazard() \
119 __asm__ __volatile__( \
121 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
124 #define tlbw_use_hazard() \
125 __asm__ __volatile__( \
127 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
130 #define back_to_back_c0_hazard() do { } while (0)
135 * Overkill warning ...
137 #define mtc0_tlbw_hazard() \
138 __asm__ __volatile__( \
139 ".set noreorder\n\t" \
140 "nop; nop; nop; nop; nop; nop;\n\t" \
143 #define tlbw_use_hazard() \
144 __asm__ __volatile__( \
145 ".set noreorder\n\t" \
146 "nop; nop; nop; nop; nop; nop;\n\t" \
152 * Interrupt enable/disable hazards
153 * Some processors have hazards when modifying
154 * the status register to change the interrupt state
157 #ifdef CONFIG_CPU_MIPSR2
160 " .macro\tirq_enable_hazard \n\t"
164 " .macro\tirq_disable_hazard \n\t"
168 " .macro\tback_to_back_c0_hazard \n\t"
172 #define irq_enable_hazard() \
173 __asm__ __volatile__( \
176 #define irq_disable_hazard() \
177 __asm__ __volatile__( \
178 "irq_disable_hazard")
180 #define back_to_back_c0_hazard() \
181 __asm__ __volatile__( \
182 "back_to_back_c0_hazard")
184 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
185 defined(CONFIG_CPU_SB1)
188 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
192 " .macro\tirq_enable_hazard \n\t"
195 " .macro\tirq_disable_hazard \n\t"
198 #define irq_enable_hazard() do { } while (0)
199 #define irq_disable_hazard() do { } while (0)
201 #define back_to_back_c0_hazard() do { } while (0)
206 * Default for classic MIPS processors. Assume worst case hazards but don't
207 * care about the irq_enable_hazard - sooner or later the hardware will
208 * enable it and we don't care when exactly.
213 " # There is a hazard but we do not care \n\t"
215 " .macro\tirq_enable_hazard \n\t"
218 " .macro\tirq_disable_hazard \n\t"
219 " _ssnop; _ssnop; _ssnop \n\t"
222 #define irq_enable_hazard() do { } while (0)
223 #define irq_disable_hazard() \
224 __asm__ __volatile__( \
225 "irq_disable_hazard")
227 #define back_to_back_c0_hazard() \
228 __asm__ __volatile__( \
229 " .set noreorder \n" \
230 " nop; nop; nop \n" \
235 #ifdef CONFIG_CPU_MIPSR2
237 * gcc has a tradition of misscompiling the previous construct using the
238 * address of a label as argument to inline assembler. Gas otoh has the
239 * annoying difference between la and dla which are only usable for 32-bit
240 * rsp. 64-bit code, so can't be used without conditional compilation.
241 * The alterantive is switching the assembler to 64-bit code which happens
242 * to work right even for 32-bit code ...
244 #define instruction_hazard() \
248 __asm__ __volatile__( \
249 " .set mips64r2 \n" \
258 #define instruction_hazard() do { } while (0)
261 #endif /* __ASSEMBLY__ */
263 #endif /* _ASM_HAZARDS_H */