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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - include/asm-mips/irqflags.h
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 #ifndef _ASM_IRQFLAGS_H
12 #define _ASM_IRQFLAGS_H
16 #include <asm/hazards.h>
19 * CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred IPIs,
20 * at the cost of branch and call overhead on each local_irq_restore()
23 #ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
25 extern void smtc_ipi_replay(void);
27 #define irq_restore_epilog(flags) \
29 if (!(flags & 0x0400)) \
35 #define irq_restore_epilog(ignore) do { } while (0)
37 #endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
40 " .macro raw_local_irq_enable \n"
44 #ifdef CONFIG_MIPS_MT_SMTC
45 " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
49 #elif defined(CONFIG_CPU_MIPSR2)
57 " irq_enable_hazard \n"
61 static inline void raw_local_irq_enable(void)
64 "raw_local_irq_enable"
71 * For cli() we have to insert nops to make sure that the new value
72 * has actually arrived in the status register before the end of this
74 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
78 * For TX49, operating only IE bit is not enough.
80 * If mfc0 $12 follows store and the mfc0 is last instruction of a
81 * page and fetching the next instruction causes TLB miss, the result
82 * of the mfc0 might wrongly contain EXL bit.
84 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
86 * Workaround: mask EXL bit of the result or place a nop before mfc0.
89 " .macro raw_local_irq_disable\n"
92 #ifdef CONFIG_MIPS_MT_SMTC
97 #elif defined(CONFIG_CPU_MIPSR2)
106 " irq_disable_hazard \n"
110 static inline void raw_local_irq_disable(void)
112 __asm__
__volatile__(
113 "raw_local_irq_disable"
120 " .macro raw_local_save_flags flags \n"
123 #ifdef CONFIG_MIPS_MT_SMTC
124 " mfc0 \\flags, $2, 1 \n"
126 " mfc0 \\flags, $12 \n"
131 #define raw_local_save_flags(x) \
132 __asm__ __volatile__( \
133 "raw_local_save_flags %0" \
137 " .macro raw_local_irq_save result \n"
141 #ifdef CONFIG_MIPS_MT_SMTC
142 " mfc0 \\result, $2, 1 \n"
143 " ori $1, \\result, 0x400 \n"
146 " andi \\result, \\result, 0x400 \n"
147 #elif defined(CONFIG_CPU_MIPSR2)
149 " andi \\result, 1 \n"
151 " mfc0 \\result, $12 \n"
152 " ori $1, \\result, 0x1f \n"
157 " irq_disable_hazard \n"
161 #define raw_local_irq_save(x) \
162 __asm__ __volatile__( \
163 "raw_local_irq_save\t%0" \
169 " .macro raw_local_irq_restore flags \n"
173 #ifdef CONFIG_MIPS_MT_SMTC
175 "andi \\flags, 0x400 \n"
179 "mtc0 \\flags, $2, 1 \n"
180 #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
182 * Slow, but doesn't suffer from a relativly unlikely race
183 * condition we're having since days 1.
185 " beqz \\flags, 1f \n"
189 #elif defined(CONFIG_CPU_MIPSR2)
191 * Fast, dangerous. Life is fun, life is good.
194 " ins $1, \\flags, 0, 1 \n"
198 " andi \\flags, 1 \n"
202 " mtc0 \\flags, $12 \n"
204 " irq_disable_hazard \n"
208 #define raw_local_irq_restore(flags) \
210 unsigned long __tmp1; \
212 __asm__ __volatile__( \
213 "raw_local_irq_restore\t%0" \
217 irq_restore_epilog(flags); \
220 static inline int raw_irqs_disabled_flags(unsigned long flags
)
222 #ifdef CONFIG_MIPS_MT_SMTC
224 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
226 return flags
& 0x400;
235 * Do the CPU's IRQ-state tracing from assembly code.
237 #ifdef CONFIG_TRACE_IRQFLAGS
238 /* Reload some registers clobbered by trace_hardirqs_on */
240 # define TRACE_IRQS_RELOAD_REGS \
241 LONG_L $11, PT_R11(sp); \
242 LONG_L $10, PT_R10(sp); \
243 LONG_L $9, PT_R9(sp); \
244 LONG_L $8, PT_R8(sp); \
245 LONG_L $7, PT_R7(sp); \
246 LONG_L $6, PT_R6(sp); \
247 LONG_L $5, PT_R5(sp); \
248 LONG_L $4, PT_R4(sp); \
251 # define TRACE_IRQS_RELOAD_REGS \
252 LONG_L $7, PT_R7(sp); \
253 LONG_L $6, PT_R6(sp); \
254 LONG_L $5, PT_R5(sp); \
255 LONG_L $4, PT_R4(sp); \
258 # define TRACE_IRQS_ON \
259 CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
260 jal trace_hardirqs_on
261 # define TRACE_IRQS_ON_RELOAD \
263 TRACE_IRQS_RELOAD_REGS
264 # define TRACE_IRQS_OFF \
265 jal trace_hardirqs_off
267 # define TRACE_IRQS_ON
268 # define TRACE_IRQS_ON_RELOAD
269 # define TRACE_IRQS_OFF
272 #endif /* _ASM_IRQFLAGS_H */