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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - include/asm-mips/irqflags.h
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 #ifndef _ASM_IRQFLAGS_H
12 #define _ASM_IRQFLAGS_H
16 #include <linux/compiler.h>
17 #include <asm/hazards.h>
20 " .macro raw_local_irq_enable \n"
24 #ifdef CONFIG_MIPS_MT_SMTC
25 " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
29 #elif defined(CONFIG_CPU_MIPSR2)
37 " irq_enable_hazard \n"
41 static inline void raw_local_irq_enable(void)
44 "raw_local_irq_enable"
51 * For cli() we have to insert nops to make sure that the new value
52 * has actually arrived in the status register before the end of this
54 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
58 * For TX49, operating only IE bit is not enough.
60 * If mfc0 $12 follows store and the mfc0 is last instruction of a
61 * page and fetching the next instruction causes TLB miss, the result
62 * of the mfc0 might wrongly contain EXL bit.
64 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
66 * Workaround: mask EXL bit of the result or place a nop before mfc0.
69 " .macro raw_local_irq_disable\n"
72 #ifdef CONFIG_MIPS_MT_SMTC
77 #elif defined(CONFIG_CPU_MIPSR2)
86 " irq_disable_hazard \n"
90 static inline void raw_local_irq_disable(void)
93 "raw_local_irq_disable"
100 " .macro raw_local_save_flags flags \n"
103 #ifdef CONFIG_MIPS_MT_SMTC
104 " mfc0 \\flags, $2, 1 \n"
106 " mfc0 \\flags, $12 \n"
111 #define raw_local_save_flags(x) \
112 __asm__ __volatile__( \
113 "raw_local_save_flags %0" \
117 " .macro raw_local_irq_save result \n"
121 #ifdef CONFIG_MIPS_MT_SMTC
122 " mfc0 \\result, $2, 1 \n"
123 " ori $1, \\result, 0x400 \n"
126 " andi \\result, \\result, 0x400 \n"
127 #elif defined(CONFIG_CPU_MIPSR2)
129 " andi \\result, 1 \n"
131 " mfc0 \\result, $12 \n"
132 " ori $1, \\result, 0x1f \n"
137 " irq_disable_hazard \n"
141 #define raw_local_irq_save(x) \
142 __asm__ __volatile__( \
143 "raw_local_irq_save\t%0" \
149 " .macro raw_local_irq_restore flags \n"
153 #ifdef CONFIG_MIPS_MT_SMTC
155 "andi \\flags, 0x400 \n"
159 "mtc0 \\flags, $2, 1 \n"
160 #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
162 * Slow, but doesn't suffer from a relativly unlikely race
163 * condition we're having since days 1.
165 " beqz \\flags, 1f \n"
169 #elif defined(CONFIG_CPU_MIPSR2)
171 * Fast, dangerous. Life is fun, life is good.
174 " ins $1, \\flags, 0, 1 \n"
178 " andi \\flags, 1 \n"
182 " mtc0 \\flags, $12 \n"
184 " irq_disable_hazard \n"
188 extern void smtc_ipi_replay(void);
190 static inline void raw_local_irq_restore(unsigned long flags
)
192 unsigned long __tmp1
;
194 #ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
196 * CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred
197 * IPIs, at the cost of branch and call overhead on each
198 * local_irq_restore()
200 if (unlikely(!(flags
& 0x0400)))
204 __asm__
__volatile__(
205 "raw_local_irq_restore\t%0"
211 static inline int raw_irqs_disabled_flags(unsigned long flags
)
213 #ifdef CONFIG_MIPS_MT_SMTC
215 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
217 return flags
& 0x400;
226 * Do the CPU's IRQ-state tracing from assembly code.
228 #ifdef CONFIG_TRACE_IRQFLAGS
229 /* Reload some registers clobbered by trace_hardirqs_on */
231 # define TRACE_IRQS_RELOAD_REGS \
232 LONG_L $11, PT_R11(sp); \
233 LONG_L $10, PT_R10(sp); \
234 LONG_L $9, PT_R9(sp); \
235 LONG_L $8, PT_R8(sp); \
236 LONG_L $7, PT_R7(sp); \
237 LONG_L $6, PT_R6(sp); \
238 LONG_L $5, PT_R5(sp); \
239 LONG_L $4, PT_R4(sp); \
242 # define TRACE_IRQS_RELOAD_REGS \
243 LONG_L $7, PT_R7(sp); \
244 LONG_L $6, PT_R6(sp); \
245 LONG_L $5, PT_R5(sp); \
246 LONG_L $4, PT_R4(sp); \
249 # define TRACE_IRQS_ON \
250 CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
251 jal trace_hardirqs_on
252 # define TRACE_IRQS_ON_RELOAD \
254 TRACE_IRQS_RELOAD_REGS
255 # define TRACE_IRQS_OFF \
256 jal trace_hardirqs_off
258 # define TRACE_IRQS_ON
259 # define TRACE_IRQS_ON_RELOAD
260 # define TRACE_IRQS_OFF
263 #endif /* _ASM_IRQFLAGS_H */