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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - include/asm-mips/irqflags.h
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 #ifndef _ASM_IRQFLAGS_H
12 #define _ASM_IRQFLAGS_H
16 #include <asm/hazards.h>
19 " .macro raw_local_irq_enable \n"
23 #ifdef CONFIG_MIPS_MT_SMTC
24 " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
28 #elif defined(CONFIG_CPU_MIPSR2)
36 " irq_enable_hazard \n"
40 static inline void raw_local_irq_enable(void)
43 "raw_local_irq_enable"
50 * For cli() we have to insert nops to make sure that the new value
51 * has actually arrived in the status register before the end of this
53 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
57 * For TX49, operating only IE bit is not enough.
59 * If mfc0 $12 follows store and the mfc0 is last instruction of a
60 * page and fetching the next instruction causes TLB miss, the result
61 * of the mfc0 might wrongly contain EXL bit.
63 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
65 * Workaround: mask EXL bit of the result or place a nop before mfc0.
68 " .macro raw_local_irq_disable\n"
71 #ifdef CONFIG_MIPS_MT_SMTC
76 #elif defined(CONFIG_CPU_MIPSR2)
85 " irq_disable_hazard \n"
89 static inline void raw_local_irq_disable(void)
92 "raw_local_irq_disable"
99 " .macro raw_local_save_flags flags \n"
102 #ifdef CONFIG_MIPS_MT_SMTC
103 " mfc0 \\flags, $2, 1 \n"
105 " mfc0 \\flags, $12 \n"
110 #define raw_local_save_flags(x) \
111 __asm__ __volatile__( \
112 "raw_local_save_flags %0" \
116 " .macro raw_local_irq_save result \n"
120 #ifdef CONFIG_MIPS_MT_SMTC
121 " mfc0 \\result, $2, 1 \n"
122 " ori $1, \\result, 0x400 \n"
125 " andi \\result, \\result, 0x400 \n"
126 #elif defined(CONFIG_CPU_MIPSR2)
128 " andi \\result, 1 \n"
130 " mfc0 \\result, $12 \n"
131 " ori $1, \\result, 0x1f \n"
136 " irq_disable_hazard \n"
140 #define raw_local_irq_save(x) \
141 __asm__ __volatile__( \
142 "raw_local_irq_save\t%0" \
148 " .macro raw_local_irq_restore flags \n"
152 #ifdef CONFIG_MIPS_MT_SMTC
154 "andi \\flags, 0x400 \n"
158 "mtc0 \\flags, $2, 1 \n"
159 #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
161 * Slow, but doesn't suffer from a relativly unlikely race
162 * condition we're having since days 1.
164 " beqz \\flags, 1f \n"
168 #elif defined(CONFIG_CPU_MIPSR2)
170 * Fast, dangerous. Life is fun, life is good.
173 " ins $1, \\flags, 0, 1 \n"
177 " andi \\flags, 1 \n"
181 " mtc0 \\flags, $12 \n"
183 " irq_disable_hazard \n"
187 #define raw_local_irq_restore(flags) \
189 unsigned long __tmp1; \
191 __asm__ __volatile__( \
192 "raw_local_irq_restore\t%0" \
198 static inline int raw_irqs_disabled_flags(unsigned long flags
)
200 #ifdef CONFIG_MIPS_MT_SMTC
202 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
204 return flags
& 0x400;
213 * Do the CPU's IRQ-state tracing from assembly code.
215 #ifdef CONFIG_TRACE_IRQFLAGS
216 /* Reload some registers clobbered by trace_hardirqs_on */
218 # define TRACE_IRQS_RELOAD_REGS \
219 LONG_L $11, PT_R11(sp); \
220 LONG_L $10, PT_R10(sp); \
221 LONG_L $9, PT_R9(sp); \
222 LONG_L $8, PT_R8(sp); \
223 LONG_L $7, PT_R7(sp); \
224 LONG_L $6, PT_R6(sp); \
225 LONG_L $5, PT_R5(sp); \
226 LONG_L $4, PT_R4(sp); \
229 # define TRACE_IRQS_RELOAD_REGS \
230 LONG_L $7, PT_R7(sp); \
231 LONG_L $6, PT_R6(sp); \
232 LONG_L $5, PT_R5(sp); \
233 LONG_L $4, PT_R4(sp); \
236 # define TRACE_IRQS_ON \
237 CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
238 jal trace_hardirqs_on
239 # define TRACE_IRQS_ON_RELOAD \
241 TRACE_IRQS_RELOAD_REGS
242 # define TRACE_IRQS_OFF \
243 jal trace_hardirqs_off
245 # define TRACE_IRQS_ON
246 # define TRACE_IRQS_ON_RELOAD
247 # define TRACE_IRQS_OFF
250 #endif /* _ASM_IRQFLAGS_H */