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Pull rework-memory-attribute-aliasing into release branch
[mirror_ubuntu-zesty-kernel.git] / include / asm-mips / mipsregs.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <asm/hazards.h>
18
19 /*
20 * The following macros are especially useful for __asm__
21 * inline assembler.
22 */
23 #ifndef __STR
24 #define __STR(x) #x
25 #endif
26 #ifndef STR
27 #define STR(x) __STR(x)
28 #endif
29
30 /*
31 * Configure language
32 */
33 #ifdef __ASSEMBLY__
34 #define _ULCAST_
35 #else
36 #define _ULCAST_ (unsigned long)
37 #endif
38
39 /*
40 * Coprocessor 0 register names
41 */
42 #define CP0_INDEX $0
43 #define CP0_RANDOM $1
44 #define CP0_ENTRYLO0 $2
45 #define CP0_ENTRYLO1 $3
46 #define CP0_CONF $3
47 #define CP0_CONTEXT $4
48 #define CP0_PAGEMASK $5
49 #define CP0_WIRED $6
50 #define CP0_INFO $7
51 #define CP0_BADVADDR $8
52 #define CP0_COUNT $9
53 #define CP0_ENTRYHI $10
54 #define CP0_COMPARE $11
55 #define CP0_STATUS $12
56 #define CP0_CAUSE $13
57 #define CP0_EPC $14
58 #define CP0_PRID $15
59 #define CP0_CONFIG $16
60 #define CP0_LLADDR $17
61 #define CP0_WATCHLO $18
62 #define CP0_WATCHHI $19
63 #define CP0_XCONTEXT $20
64 #define CP0_FRAMEMASK $21
65 #define CP0_DIAGNOSTIC $22
66 #define CP0_DEBUG $23
67 #define CP0_DEPC $24
68 #define CP0_PERFORMANCE $25
69 #define CP0_ECC $26
70 #define CP0_CACHEERR $27
71 #define CP0_TAGLO $28
72 #define CP0_TAGHI $29
73 #define CP0_ERROREPC $30
74 #define CP0_DESAVE $31
75
76 /*
77 * R4640/R4650 cp0 register names. These registers are listed
78 * here only for completeness; without MMU these CPUs are not useable
79 * by Linux. A future ELKS port might take make Linux run on them
80 * though ...
81 */
82 #define CP0_IBASE $0
83 #define CP0_IBOUND $1
84 #define CP0_DBASE $2
85 #define CP0_DBOUND $3
86 #define CP0_CALG $17
87 #define CP0_IWATCH $18
88 #define CP0_DWATCH $19
89
90 /*
91 * Coprocessor 0 Set 1 register names
92 */
93 #define CP0_S1_DERRADDR0 $26
94 #define CP0_S1_DERRADDR1 $27
95 #define CP0_S1_INTCONTROL $20
96
97 /*
98 * Coprocessor 0 Set 2 register names
99 */
100 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
101
102 /*
103 * Coprocessor 0 Set 3 register names
104 */
105 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
106
107 /*
108 * TX39 Series
109 */
110 #define CP0_TX39_CACHE $7
111
112 /*
113 * Coprocessor 1 (FPU) register names
114 */
115 #define CP1_REVISION $0
116 #define CP1_STATUS $31
117
118 /*
119 * FPU Status Register Values
120 */
121 /*
122 * Status Register Values
123 */
124
125 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
126 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
127 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
128 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
129 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
130 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
131 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
132 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
133 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
134 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
135
136 /*
137 * X the exception cause indicator
138 * E the exception enable
139 * S the sticky/flag bit
140 */
141 #define FPU_CSR_ALL_X 0x0003f000
142 #define FPU_CSR_UNI_X 0x00020000
143 #define FPU_CSR_INV_X 0x00010000
144 #define FPU_CSR_DIV_X 0x00008000
145 #define FPU_CSR_OVF_X 0x00004000
146 #define FPU_CSR_UDF_X 0x00002000
147 #define FPU_CSR_INE_X 0x00001000
148
149 #define FPU_CSR_ALL_E 0x00000f80
150 #define FPU_CSR_INV_E 0x00000800
151 #define FPU_CSR_DIV_E 0x00000400
152 #define FPU_CSR_OVF_E 0x00000200
153 #define FPU_CSR_UDF_E 0x00000100
154 #define FPU_CSR_INE_E 0x00000080
155
156 #define FPU_CSR_ALL_S 0x0000007c
157 #define FPU_CSR_INV_S 0x00000040
158 #define FPU_CSR_DIV_S 0x00000020
159 #define FPU_CSR_OVF_S 0x00000010
160 #define FPU_CSR_UDF_S 0x00000008
161 #define FPU_CSR_INE_S 0x00000004
162
163 /* rounding mode */
164 #define FPU_CSR_RN 0x0 /* nearest */
165 #define FPU_CSR_RZ 0x1 /* towards zero */
166 #define FPU_CSR_RU 0x2 /* towards +Infinity */
167 #define FPU_CSR_RD 0x3 /* towards -Infinity */
168
169
170 /*
171 * Values for PageMask register
172 */
173 #ifdef CONFIG_CPU_VR41XX
174
175 /* Why doesn't stupidity hurt ... */
176
177 #define PM_1K 0x00000000
178 #define PM_4K 0x00001800
179 #define PM_16K 0x00007800
180 #define PM_64K 0x0001f800
181 #define PM_256K 0x0007f800
182
183 #else
184
185 #define PM_4K 0x00000000
186 #define PM_16K 0x00006000
187 #define PM_64K 0x0001e000
188 #define PM_256K 0x0007e000
189 #define PM_1M 0x001fe000
190 #define PM_4M 0x007fe000
191 #define PM_16M 0x01ffe000
192 #define PM_64M 0x07ffe000
193 #define PM_256M 0x1fffe000
194
195 #endif
196
197 /*
198 * Default page size for a given kernel configuration
199 */
200 #ifdef CONFIG_PAGE_SIZE_4KB
201 #define PM_DEFAULT_MASK PM_4K
202 #elif defined(CONFIG_PAGE_SIZE_16KB)
203 #define PM_DEFAULT_MASK PM_16K
204 #elif defined(CONFIG_PAGE_SIZE_64KB)
205 #define PM_DEFAULT_MASK PM_64K
206 #else
207 #error Bad page size configuration!
208 #endif
209
210
211 /*
212 * Values used for computation of new tlb entries
213 */
214 #define PL_4K 12
215 #define PL_16K 14
216 #define PL_64K 16
217 #define PL_256K 18
218 #define PL_1M 20
219 #define PL_4M 22
220 #define PL_16M 24
221 #define PL_64M 26
222 #define PL_256M 28
223
224 /*
225 * R4x00 interrupt enable / cause bits
226 */
227 #define IE_SW0 (_ULCAST_(1) << 8)
228 #define IE_SW1 (_ULCAST_(1) << 9)
229 #define IE_IRQ0 (_ULCAST_(1) << 10)
230 #define IE_IRQ1 (_ULCAST_(1) << 11)
231 #define IE_IRQ2 (_ULCAST_(1) << 12)
232 #define IE_IRQ3 (_ULCAST_(1) << 13)
233 #define IE_IRQ4 (_ULCAST_(1) << 14)
234 #define IE_IRQ5 (_ULCAST_(1) << 15)
235
236 /*
237 * R4x00 interrupt cause bits
238 */
239 #define C_SW0 (_ULCAST_(1) << 8)
240 #define C_SW1 (_ULCAST_(1) << 9)
241 #define C_IRQ0 (_ULCAST_(1) << 10)
242 #define C_IRQ1 (_ULCAST_(1) << 11)
243 #define C_IRQ2 (_ULCAST_(1) << 12)
244 #define C_IRQ3 (_ULCAST_(1) << 13)
245 #define C_IRQ4 (_ULCAST_(1) << 14)
246 #define C_IRQ5 (_ULCAST_(1) << 15)
247
248 /*
249 * Bitfields in the R4xx0 cp0 status register
250 */
251 #define ST0_IE 0x00000001
252 #define ST0_EXL 0x00000002
253 #define ST0_ERL 0x00000004
254 #define ST0_KSU 0x00000018
255 # define KSU_USER 0x00000010
256 # define KSU_SUPERVISOR 0x00000008
257 # define KSU_KERNEL 0x00000000
258 #define ST0_UX 0x00000020
259 #define ST0_SX 0x00000040
260 #define ST0_KX 0x00000080
261 #define ST0_DE 0x00010000
262 #define ST0_CE 0x00020000
263
264 /*
265 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
266 * cacheops in userspace. This bit exists only on RM7000 and RM9000
267 * processors.
268 */
269 #define ST0_CO 0x08000000
270
271 /*
272 * Bitfields in the R[23]000 cp0 status register.
273 */
274 #define ST0_IEC 0x00000001
275 #define ST0_KUC 0x00000002
276 #define ST0_IEP 0x00000004
277 #define ST0_KUP 0x00000008
278 #define ST0_IEO 0x00000010
279 #define ST0_KUO 0x00000020
280 /* bits 6 & 7 are reserved on R[23]000 */
281 #define ST0_ISC 0x00010000
282 #define ST0_SWC 0x00020000
283 #define ST0_CM 0x00080000
284
285 /*
286 * Bits specific to the R4640/R4650
287 */
288 #define ST0_UM (_ULCAST_(1) << 4)
289 #define ST0_IL (_ULCAST_(1) << 23)
290 #define ST0_DL (_ULCAST_(1) << 24)
291
292 /*
293 * Enable the MIPS MDMX and DSP ASEs
294 */
295 #define ST0_MX 0x01000000
296
297 /*
298 * Bitfields in the TX39 family CP0 Configuration Register 3
299 */
300 #define TX39_CONF_ICS_SHIFT 19
301 #define TX39_CONF_ICS_MASK 0x00380000
302 #define TX39_CONF_ICS_1KB 0x00000000
303 #define TX39_CONF_ICS_2KB 0x00080000
304 #define TX39_CONF_ICS_4KB 0x00100000
305 #define TX39_CONF_ICS_8KB 0x00180000
306 #define TX39_CONF_ICS_16KB 0x00200000
307
308 #define TX39_CONF_DCS_SHIFT 16
309 #define TX39_CONF_DCS_MASK 0x00070000
310 #define TX39_CONF_DCS_1KB 0x00000000
311 #define TX39_CONF_DCS_2KB 0x00010000
312 #define TX39_CONF_DCS_4KB 0x00020000
313 #define TX39_CONF_DCS_8KB 0x00030000
314 #define TX39_CONF_DCS_16KB 0x00040000
315
316 #define TX39_CONF_CWFON 0x00004000
317 #define TX39_CONF_WBON 0x00002000
318 #define TX39_CONF_RF_SHIFT 10
319 #define TX39_CONF_RF_MASK 0x00000c00
320 #define TX39_CONF_DOZE 0x00000200
321 #define TX39_CONF_HALT 0x00000100
322 #define TX39_CONF_LOCK 0x00000080
323 #define TX39_CONF_ICE 0x00000020
324 #define TX39_CONF_DCE 0x00000010
325 #define TX39_CONF_IRSIZE_SHIFT 2
326 #define TX39_CONF_IRSIZE_MASK 0x0000000c
327 #define TX39_CONF_DRSIZE_SHIFT 0
328 #define TX39_CONF_DRSIZE_MASK 0x00000003
329
330 /*
331 * Status register bits available in all MIPS CPUs.
332 */
333 #define ST0_IM 0x0000ff00
334 #define STATUSB_IP0 8
335 #define STATUSF_IP0 (_ULCAST_(1) << 8)
336 #define STATUSB_IP1 9
337 #define STATUSF_IP1 (_ULCAST_(1) << 9)
338 #define STATUSB_IP2 10
339 #define STATUSF_IP2 (_ULCAST_(1) << 10)
340 #define STATUSB_IP3 11
341 #define STATUSF_IP3 (_ULCAST_(1) << 11)
342 #define STATUSB_IP4 12
343 #define STATUSF_IP4 (_ULCAST_(1) << 12)
344 #define STATUSB_IP5 13
345 #define STATUSF_IP5 (_ULCAST_(1) << 13)
346 #define STATUSB_IP6 14
347 #define STATUSF_IP6 (_ULCAST_(1) << 14)
348 #define STATUSB_IP7 15
349 #define STATUSF_IP7 (_ULCAST_(1) << 15)
350 #define STATUSB_IP8 0
351 #define STATUSF_IP8 (_ULCAST_(1) << 0)
352 #define STATUSB_IP9 1
353 #define STATUSF_IP9 (_ULCAST_(1) << 1)
354 #define STATUSB_IP10 2
355 #define STATUSF_IP10 (_ULCAST_(1) << 2)
356 #define STATUSB_IP11 3
357 #define STATUSF_IP11 (_ULCAST_(1) << 3)
358 #define STATUSB_IP12 4
359 #define STATUSF_IP12 (_ULCAST_(1) << 4)
360 #define STATUSB_IP13 5
361 #define STATUSF_IP13 (_ULCAST_(1) << 5)
362 #define STATUSB_IP14 6
363 #define STATUSF_IP14 (_ULCAST_(1) << 6)
364 #define STATUSB_IP15 7
365 #define STATUSF_IP15 (_ULCAST_(1) << 7)
366 #define ST0_CH 0x00040000
367 #define ST0_SR 0x00100000
368 #define ST0_TS 0x00200000
369 #define ST0_BEV 0x00400000
370 #define ST0_RE 0x02000000
371 #define ST0_FR 0x04000000
372 #define ST0_CU 0xf0000000
373 #define ST0_CU0 0x10000000
374 #define ST0_CU1 0x20000000
375 #define ST0_CU2 0x40000000
376 #define ST0_CU3 0x80000000
377 #define ST0_XX 0x80000000 /* MIPS IV naming */
378
379 /*
380 * Bitfields and bit numbers in the coprocessor 0 cause register.
381 *
382 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
383 */
384 #define CAUSEB_EXCCODE 2
385 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
386 #define CAUSEB_IP 8
387 #define CAUSEF_IP (_ULCAST_(255) << 8)
388 #define CAUSEB_IP0 8
389 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
390 #define CAUSEB_IP1 9
391 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
392 #define CAUSEB_IP2 10
393 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
394 #define CAUSEB_IP3 11
395 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
396 #define CAUSEB_IP4 12
397 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
398 #define CAUSEB_IP5 13
399 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
400 #define CAUSEB_IP6 14
401 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
402 #define CAUSEB_IP7 15
403 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
404 #define CAUSEB_IV 23
405 #define CAUSEF_IV (_ULCAST_(1) << 23)
406 #define CAUSEB_CE 28
407 #define CAUSEF_CE (_ULCAST_(3) << 28)
408 #define CAUSEB_BD 31
409 #define CAUSEF_BD (_ULCAST_(1) << 31)
410
411 /*
412 * Bits in the coprocessor 0 config register.
413 */
414 /* Generic bits. */
415 #define CONF_CM_CACHABLE_NO_WA 0
416 #define CONF_CM_CACHABLE_WA 1
417 #define CONF_CM_UNCACHED 2
418 #define CONF_CM_CACHABLE_NONCOHERENT 3
419 #define CONF_CM_CACHABLE_CE 4
420 #define CONF_CM_CACHABLE_COW 5
421 #define CONF_CM_CACHABLE_CUW 6
422 #define CONF_CM_CACHABLE_ACCELERATED 7
423 #define CONF_CM_CMASK 7
424 #define CONF_BE (_ULCAST_(1) << 15)
425
426 /* Bits common to various processors. */
427 #define CONF_CU (_ULCAST_(1) << 3)
428 #define CONF_DB (_ULCAST_(1) << 4)
429 #define CONF_IB (_ULCAST_(1) << 5)
430 #define CONF_DC (_ULCAST_(7) << 6)
431 #define CONF_IC (_ULCAST_(7) << 9)
432 #define CONF_EB (_ULCAST_(1) << 13)
433 #define CONF_EM (_ULCAST_(1) << 14)
434 #define CONF_SM (_ULCAST_(1) << 16)
435 #define CONF_SC (_ULCAST_(1) << 17)
436 #define CONF_EW (_ULCAST_(3) << 18)
437 #define CONF_EP (_ULCAST_(15)<< 24)
438 #define CONF_EC (_ULCAST_(7) << 28)
439 #define CONF_CM (_ULCAST_(1) << 31)
440
441 /* Bits specific to the R4xx0. */
442 #define R4K_CONF_SW (_ULCAST_(1) << 20)
443 #define R4K_CONF_SS (_ULCAST_(1) << 21)
444 #define R4K_CONF_SB (_ULCAST_(3) << 22)
445
446 /* Bits specific to the R5000. */
447 #define R5K_CONF_SE (_ULCAST_(1) << 12)
448 #define R5K_CONF_SS (_ULCAST_(3) << 20)
449
450 /* Bits specific to the RM7000. */
451 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
452 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
453 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
454 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
455 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
456 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
457
458 /* Bits specific to the R10000. */
459 #define R10K_CONF_DN (_ULCAST_(3) << 3)
460 #define R10K_CONF_CT (_ULCAST_(1) << 5)
461 #define R10K_CONF_PE (_ULCAST_(1) << 6)
462 #define R10K_CONF_PM (_ULCAST_(3) << 7)
463 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
464 #define R10K_CONF_SB (_ULCAST_(1) << 13)
465 #define R10K_CONF_SK (_ULCAST_(1) << 14)
466 #define R10K_CONF_SS (_ULCAST_(7) << 16)
467 #define R10K_CONF_SC (_ULCAST_(7) << 19)
468 #define R10K_CONF_DC (_ULCAST_(7) << 26)
469 #define R10K_CONF_IC (_ULCAST_(7) << 29)
470
471 /* Bits specific to the VR41xx. */
472 #define VR41_CONF_CS (_ULCAST_(1) << 12)
473 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
474 #define VR41_CONF_AD (_ULCAST_(1) << 23)
475
476 /* Bits specific to the R30xx. */
477 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
478 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
479 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
480 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
481 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
482 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
483 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
484 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
485 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
486
487 /* Bits specific to the TX49. */
488 #define TX49_CONF_DC (_ULCAST_(1) << 16)
489 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
490 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
491 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
492
493 /* Bits specific to the MIPS32/64 PRA. */
494 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
495 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
496 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
497 #define MIPS_CONF_M (_ULCAST_(1) << 31)
498
499 /*
500 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
501 */
502 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
503 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
504 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
505 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
506 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
507 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
508 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
509 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
510 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
511 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
512 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
513 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
514 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
515 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
516
517 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
518 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
519 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
520 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
521 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
522 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
523 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
524 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
525
526 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
527 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
528 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
529 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
530 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
531 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
532 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
533 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
534
535 /*
536 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
537 */
538 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
539 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
540 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
541 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
542 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
543 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
544 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
545
546 /*
547 * R10000 performance counter definitions.
548 *
549 * FIXME: The R10000 performance counter opens a nice way to implement CPU
550 * time accounting with a precission of one cycle. I don't have
551 * R10000 silicon but just a manual, so ...
552 */
553
554 /*
555 * Events counted by counter #0
556 */
557 #define CE0_CYCLES 0
558 #define CE0_INSN_ISSUED 1
559 #define CE0_LPSC_ISSUED 2
560 #define CE0_S_ISSUED 3
561 #define CE0_SC_ISSUED 4
562 #define CE0_SC_FAILED 5
563 #define CE0_BRANCH_DECODED 6
564 #define CE0_QW_WB_SECONDARY 7
565 #define CE0_CORRECTED_ECC_ERRORS 8
566 #define CE0_ICACHE_MISSES 9
567 #define CE0_SCACHE_I_MISSES 10
568 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
569 #define CE0_EXT_INTERVENTIONS_REQ 12
570 #define CE0_EXT_INVALIDATE_REQ 13
571 #define CE0_VIRTUAL_COHERENCY_COND 14
572 #define CE0_INSN_GRADUATED 15
573
574 /*
575 * Events counted by counter #1
576 */
577 #define CE1_CYCLES 0
578 #define CE1_INSN_GRADUATED 1
579 #define CE1_LPSC_GRADUATED 2
580 #define CE1_S_GRADUATED 3
581 #define CE1_SC_GRADUATED 4
582 #define CE1_FP_INSN_GRADUATED 5
583 #define CE1_QW_WB_PRIMARY 6
584 #define CE1_TLB_REFILL 7
585 #define CE1_BRANCH_MISSPREDICTED 8
586 #define CE1_DCACHE_MISS 9
587 #define CE1_SCACHE_D_MISSES 10
588 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
589 #define CE1_EXT_INTERVENTION_HITS 12
590 #define CE1_EXT_INVALIDATE_REQ 13
591 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
592 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
593
594 /*
595 * These flags define in which privilege mode the counters count events
596 */
597 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
598 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
599 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
600 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
601
602 #ifndef __ASSEMBLY__
603
604 /*
605 * Functions to access the R10000 performance counters. These are basically
606 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
607 * performance counter number encoded into bits 1 ... 5 of the instruction.
608 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
609 * disassembler these will look like an access to sel 0 or 1.
610 */
611 #define read_r10k_perf_cntr(counter) \
612 ({ \
613 unsigned int __res; \
614 __asm__ __volatile__( \
615 "mfpc\t%0, %1" \
616 : "=r" (__res) \
617 : "i" (counter)); \
618 \
619 __res; \
620 })
621
622 #define write_r10k_perf_cntr(counter,val) \
623 do { \
624 __asm__ __volatile__( \
625 "mtpc\t%0, %1" \
626 : \
627 : "r" (val), "i" (counter)); \
628 } while (0)
629
630 #define read_r10k_perf_event(counter) \
631 ({ \
632 unsigned int __res; \
633 __asm__ __volatile__( \
634 "mfps\t%0, %1" \
635 : "=r" (__res) \
636 : "i" (counter)); \
637 \
638 __res; \
639 })
640
641 #define write_r10k_perf_cntl(counter,val) \
642 do { \
643 __asm__ __volatile__( \
644 "mtps\t%0, %1" \
645 : \
646 : "r" (val), "i" (counter)); \
647 } while (0)
648
649
650 /*
651 * Macros to access the system control coprocessor
652 */
653
654 #define __read_32bit_c0_register(source, sel) \
655 ({ int __res; \
656 if (sel == 0) \
657 __asm__ __volatile__( \
658 "mfc0\t%0, " #source "\n\t" \
659 : "=r" (__res)); \
660 else \
661 __asm__ __volatile__( \
662 ".set\tmips32\n\t" \
663 "mfc0\t%0, " #source ", " #sel "\n\t" \
664 ".set\tmips0\n\t" \
665 : "=r" (__res)); \
666 __res; \
667 })
668
669 #define __read_64bit_c0_register(source, sel) \
670 ({ unsigned long long __res; \
671 if (sizeof(unsigned long) == 4) \
672 __res = __read_64bit_c0_split(source, sel); \
673 else if (sel == 0) \
674 __asm__ __volatile__( \
675 ".set\tmips3\n\t" \
676 "dmfc0\t%0, " #source "\n\t" \
677 ".set\tmips0" \
678 : "=r" (__res)); \
679 else \
680 __asm__ __volatile__( \
681 ".set\tmips64\n\t" \
682 "dmfc0\t%0, " #source ", " #sel "\n\t" \
683 ".set\tmips0" \
684 : "=r" (__res)); \
685 __res; \
686 })
687
688 #define __write_32bit_c0_register(register, sel, value) \
689 do { \
690 if (sel == 0) \
691 __asm__ __volatile__( \
692 "mtc0\t%z0, " #register "\n\t" \
693 : : "Jr" ((unsigned int)(value))); \
694 else \
695 __asm__ __volatile__( \
696 ".set\tmips32\n\t" \
697 "mtc0\t%z0, " #register ", " #sel "\n\t" \
698 ".set\tmips0" \
699 : : "Jr" ((unsigned int)(value))); \
700 } while (0)
701
702 #define __write_64bit_c0_register(register, sel, value) \
703 do { \
704 if (sizeof(unsigned long) == 4) \
705 __write_64bit_c0_split(register, sel, value); \
706 else if (sel == 0) \
707 __asm__ __volatile__( \
708 ".set\tmips3\n\t" \
709 "dmtc0\t%z0, " #register "\n\t" \
710 ".set\tmips0" \
711 : : "Jr" (value)); \
712 else \
713 __asm__ __volatile__( \
714 ".set\tmips64\n\t" \
715 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
716 ".set\tmips0" \
717 : : "Jr" (value)); \
718 } while (0)
719
720 #define __read_ulong_c0_register(reg, sel) \
721 ((sizeof(unsigned long) == 4) ? \
722 (unsigned long) __read_32bit_c0_register(reg, sel) : \
723 (unsigned long) __read_64bit_c0_register(reg, sel))
724
725 #define __write_ulong_c0_register(reg, sel, val) \
726 do { \
727 if (sizeof(unsigned long) == 4) \
728 __write_32bit_c0_register(reg, sel, val); \
729 else \
730 __write_64bit_c0_register(reg, sel, val); \
731 } while (0)
732
733 /*
734 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
735 */
736 #define __read_32bit_c0_ctrl_register(source) \
737 ({ int __res; \
738 __asm__ __volatile__( \
739 "cfc0\t%0, " #source "\n\t" \
740 : "=r" (__res)); \
741 __res; \
742 })
743
744 #define __write_32bit_c0_ctrl_register(register, value) \
745 do { \
746 __asm__ __volatile__( \
747 "ctc0\t%z0, " #register "\n\t" \
748 : : "Jr" ((unsigned int)(value))); \
749 } while (0)
750
751 /*
752 * These versions are only needed for systems with more than 38 bits of
753 * physical address space running the 32-bit kernel. That's none atm :-)
754 */
755 #define __read_64bit_c0_split(source, sel) \
756 ({ \
757 unsigned long long val; \
758 unsigned long flags; \
759 \
760 local_irq_save(flags); \
761 if (sel == 0) \
762 __asm__ __volatile__( \
763 ".set\tmips64\n\t" \
764 "dmfc0\t%M0, " #source "\n\t" \
765 "dsll\t%L0, %M0, 32\n\t" \
766 "dsrl\t%M0, %M0, 32\n\t" \
767 "dsrl\t%L0, %L0, 32\n\t" \
768 ".set\tmips0" \
769 : "=r" (val)); \
770 else \
771 __asm__ __volatile__( \
772 ".set\tmips64\n\t" \
773 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
774 "dsll\t%L0, %M0, 32\n\t" \
775 "dsrl\t%M0, %M0, 32\n\t" \
776 "dsrl\t%L0, %L0, 32\n\t" \
777 ".set\tmips0" \
778 : "=r" (val)); \
779 local_irq_restore(flags); \
780 \
781 val; \
782 })
783
784 #define __write_64bit_c0_split(source, sel, val) \
785 do { \
786 unsigned long flags; \
787 \
788 local_irq_save(flags); \
789 if (sel == 0) \
790 __asm__ __volatile__( \
791 ".set\tmips64\n\t" \
792 "dsll\t%L0, %L0, 32\n\t" \
793 "dsrl\t%L0, %L0, 32\n\t" \
794 "dsll\t%M0, %M0, 32\n\t" \
795 "or\t%L0, %L0, %M0\n\t" \
796 "dmtc0\t%L0, " #source "\n\t" \
797 ".set\tmips0" \
798 : : "r" (val)); \
799 else \
800 __asm__ __volatile__( \
801 ".set\tmips64\n\t" \
802 "dsll\t%L0, %L0, 32\n\t" \
803 "dsrl\t%L0, %L0, 32\n\t" \
804 "dsll\t%M0, %M0, 32\n\t" \
805 "or\t%L0, %L0, %M0\n\t" \
806 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
807 ".set\tmips0" \
808 : : "r" (val)); \
809 local_irq_restore(flags); \
810 } while (0)
811
812 #define read_c0_index() __read_32bit_c0_register($0, 0)
813 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
814
815 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
816 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
817
818 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
819 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
820
821 #define read_c0_conf() __read_32bit_c0_register($3, 0)
822 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
823
824 #define read_c0_context() __read_ulong_c0_register($4, 0)
825 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
826
827 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
828 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
829
830 #define read_c0_wired() __read_32bit_c0_register($6, 0)
831 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
832
833 #define read_c0_info() __read_32bit_c0_register($7, 0)
834
835 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
836 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
837
838 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
839 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
840
841 #define read_c0_count() __read_32bit_c0_register($9, 0)
842 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
843
844 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
845 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
846
847 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
848 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
849
850 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
851 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
852
853 #define read_c0_compare() __read_32bit_c0_register($11, 0)
854 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
855
856 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
857 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
858
859 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
860 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
861
862 #define read_c0_status() __read_32bit_c0_register($12, 0)
863 #ifdef CONFIG_MIPS_MT_SMTC
864 #define write_c0_status(val) \
865 do { \
866 __write_32bit_c0_register($12, 0, val); \
867 __ehb(); \
868 } while (0)
869 #else
870 /*
871 * Legacy non-SMTC code, which may be hazardous
872 * but which might not support EHB
873 */
874 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
875 #endif /* CONFIG_MIPS_MT_SMTC */
876
877 #define read_c0_cause() __read_32bit_c0_register($13, 0)
878 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
879
880 #define read_c0_epc() __read_ulong_c0_register($14, 0)
881 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
882
883 #define read_c0_prid() __read_32bit_c0_register($15, 0)
884
885 #define read_c0_config() __read_32bit_c0_register($16, 0)
886 #define read_c0_config1() __read_32bit_c0_register($16, 1)
887 #define read_c0_config2() __read_32bit_c0_register($16, 2)
888 #define read_c0_config3() __read_32bit_c0_register($16, 3)
889 #define read_c0_config4() __read_32bit_c0_register($16, 4)
890 #define read_c0_config5() __read_32bit_c0_register($16, 5)
891 #define read_c0_config6() __read_32bit_c0_register($16, 6)
892 #define read_c0_config7() __read_32bit_c0_register($16, 7)
893 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
894 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
895 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
896 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
897 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
898 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
899 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
900 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
901
902 /*
903 * The WatchLo register. There may be upto 8 of them.
904 */
905 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
906 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
907 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
908 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
909 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
910 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
911 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
912 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
913 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
914 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
915 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
916 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
917 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
918 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
919 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
920 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
921
922 /*
923 * The WatchHi register. There may be upto 8 of them.
924 */
925 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
926 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
927 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
928 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
929 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
930 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
931 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
932 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
933
934 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
935 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
936 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
937 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
938 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
939 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
940 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
941 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
942
943 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
944 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
945
946 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
947 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
948
949 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
950 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
951
952 /* RM9000 PerfControl performance counter control register */
953 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
954 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
955
956 #define read_c0_diag() __read_32bit_c0_register($22, 0)
957 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
958
959 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
960 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
961
962 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
963 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
964
965 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
966 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
967
968 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
969 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
970
971 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
972 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
973
974 #define read_c0_debug() __read_32bit_c0_register($23, 0)
975 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
976
977 #define read_c0_depc() __read_ulong_c0_register($24, 0)
978 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
979
980 /*
981 * MIPS32 / MIPS64 performance counters
982 */
983 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
984 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
985 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
986 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
987 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
988 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
989 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
990 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
991 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
992 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
993 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
994 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
995 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
996 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
997 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
998 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
999
1000 /* RM9000 PerfCount performance counter register */
1001 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
1002 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
1003
1004 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1005 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1006
1007 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1008 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1009
1010 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1011
1012 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1013 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1014
1015 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1016 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1017
1018 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1019 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1020
1021 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1022 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1023
1024 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1025 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1026
1027 /* MIPSR2 */
1028 #define read_c0_hwrena() __read_32bit_c0_register($7,0)
1029 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1030
1031 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1032 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1033
1034 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1035 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1036
1037 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1038 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1039
1040 #define read_c0_ebase() __read_32bit_c0_register($15,1)
1041 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1042
1043 /*
1044 * Macros to access the floating point coprocessor control registers
1045 */
1046 #define read_32bit_cp1_register(source) \
1047 ({ int __res; \
1048 __asm__ __volatile__( \
1049 ".set\tpush\n\t" \
1050 ".set\treorder\n\t" \
1051 "cfc1\t%0,"STR(source)"\n\t" \
1052 ".set\tpop" \
1053 : "=r" (__res)); \
1054 __res;})
1055
1056 #define rddsp(mask) \
1057 ({ \
1058 unsigned int __res; \
1059 \
1060 __asm__ __volatile__( \
1061 " .set push \n" \
1062 " .set noat \n" \
1063 " # rddsp $1, %x1 \n" \
1064 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1065 " move %0, $1 \n" \
1066 " .set pop \n" \
1067 : "=r" (__res) \
1068 : "i" (mask)); \
1069 __res; \
1070 })
1071
1072 #define wrdsp(val, mask) \
1073 do { \
1074 __asm__ __volatile__( \
1075 " .set push \n" \
1076 " .set noat \n" \
1077 " move $1, %0 \n" \
1078 " # wrdsp $1, %x1 \n" \
1079 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1080 " .set pop \n" \
1081 : \
1082 : "r" (val), "i" (mask)); \
1083 } while (0)
1084
1085 #if 0 /* Need DSP ASE capable assembler ... */
1086 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1087 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1088 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1089 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1090
1091 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1092 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1093 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1094 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1095
1096 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1097 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1098 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1099 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1100
1101 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1102 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1103 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1104 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1105
1106 #else
1107
1108 #define mfhi0() \
1109 ({ \
1110 unsigned long __treg; \
1111 \
1112 __asm__ __volatile__( \
1113 " .set push \n" \
1114 " .set noat \n" \
1115 " # mfhi %0, $ac0 \n" \
1116 " .word 0x00000810 \n" \
1117 " move %0, $1 \n" \
1118 " .set pop \n" \
1119 : "=r" (__treg)); \
1120 __treg; \
1121 })
1122
1123 #define mfhi1() \
1124 ({ \
1125 unsigned long __treg; \
1126 \
1127 __asm__ __volatile__( \
1128 " .set push \n" \
1129 " .set noat \n" \
1130 " # mfhi %0, $ac1 \n" \
1131 " .word 0x00200810 \n" \
1132 " move %0, $1 \n" \
1133 " .set pop \n" \
1134 : "=r" (__treg)); \
1135 __treg; \
1136 })
1137
1138 #define mfhi2() \
1139 ({ \
1140 unsigned long __treg; \
1141 \
1142 __asm__ __volatile__( \
1143 " .set push \n" \
1144 " .set noat \n" \
1145 " # mfhi %0, $ac2 \n" \
1146 " .word 0x00400810 \n" \
1147 " move %0, $1 \n" \
1148 " .set pop \n" \
1149 : "=r" (__treg)); \
1150 __treg; \
1151 })
1152
1153 #define mfhi3() \
1154 ({ \
1155 unsigned long __treg; \
1156 \
1157 __asm__ __volatile__( \
1158 " .set push \n" \
1159 " .set noat \n" \
1160 " # mfhi %0, $ac3 \n" \
1161 " .word 0x00600810 \n" \
1162 " move %0, $1 \n" \
1163 " .set pop \n" \
1164 : "=r" (__treg)); \
1165 __treg; \
1166 })
1167
1168 #define mflo0() \
1169 ({ \
1170 unsigned long __treg; \
1171 \
1172 __asm__ __volatile__( \
1173 " .set push \n" \
1174 " .set noat \n" \
1175 " # mflo %0, $ac0 \n" \
1176 " .word 0x00000812 \n" \
1177 " move %0, $1 \n" \
1178 " .set pop \n" \
1179 : "=r" (__treg)); \
1180 __treg; \
1181 })
1182
1183 #define mflo1() \
1184 ({ \
1185 unsigned long __treg; \
1186 \
1187 __asm__ __volatile__( \
1188 " .set push \n" \
1189 " .set noat \n" \
1190 " # mflo %0, $ac1 \n" \
1191 " .word 0x00200812 \n" \
1192 " move %0, $1 \n" \
1193 " .set pop \n" \
1194 : "=r" (__treg)); \
1195 __treg; \
1196 })
1197
1198 #define mflo2() \
1199 ({ \
1200 unsigned long __treg; \
1201 \
1202 __asm__ __volatile__( \
1203 " .set push \n" \
1204 " .set noat \n" \
1205 " # mflo %0, $ac2 \n" \
1206 " .word 0x00400812 \n" \
1207 " move %0, $1 \n" \
1208 " .set pop \n" \
1209 : "=r" (__treg)); \
1210 __treg; \
1211 })
1212
1213 #define mflo3() \
1214 ({ \
1215 unsigned long __treg; \
1216 \
1217 __asm__ __volatile__( \
1218 " .set push \n" \
1219 " .set noat \n" \
1220 " # mflo %0, $ac3 \n" \
1221 " .word 0x00600812 \n" \
1222 " move %0, $1 \n" \
1223 " .set pop \n" \
1224 : "=r" (__treg)); \
1225 __treg; \
1226 })
1227
1228 #define mthi0(x) \
1229 do { \
1230 __asm__ __volatile__( \
1231 " .set push \n" \
1232 " .set noat \n" \
1233 " move $1, %0 \n" \
1234 " # mthi $1, $ac0 \n" \
1235 " .word 0x00200011 \n" \
1236 " .set pop \n" \
1237 : \
1238 : "r" (x)); \
1239 } while (0)
1240
1241 #define mthi1(x) \
1242 do { \
1243 __asm__ __volatile__( \
1244 " .set push \n" \
1245 " .set noat \n" \
1246 " move $1, %0 \n" \
1247 " # mthi $1, $ac1 \n" \
1248 " .word 0x00200811 \n" \
1249 " .set pop \n" \
1250 : \
1251 : "r" (x)); \
1252 } while (0)
1253
1254 #define mthi2(x) \
1255 do { \
1256 __asm__ __volatile__( \
1257 " .set push \n" \
1258 " .set noat \n" \
1259 " move $1, %0 \n" \
1260 " # mthi $1, $ac2 \n" \
1261 " .word 0x00201011 \n" \
1262 " .set pop \n" \
1263 : \
1264 : "r" (x)); \
1265 } while (0)
1266
1267 #define mthi3(x) \
1268 do { \
1269 __asm__ __volatile__( \
1270 " .set push \n" \
1271 " .set noat \n" \
1272 " move $1, %0 \n" \
1273 " # mthi $1, $ac3 \n" \
1274 " .word 0x00201811 \n" \
1275 " .set pop \n" \
1276 : \
1277 : "r" (x)); \
1278 } while (0)
1279
1280 #define mtlo0(x) \
1281 do { \
1282 __asm__ __volatile__( \
1283 " .set push \n" \
1284 " .set noat \n" \
1285 " move $1, %0 \n" \
1286 " # mtlo $1, $ac0 \n" \
1287 " .word 0x00200013 \n" \
1288 " .set pop \n" \
1289 : \
1290 : "r" (x)); \
1291 } while (0)
1292
1293 #define mtlo1(x) \
1294 do { \
1295 __asm__ __volatile__( \
1296 " .set push \n" \
1297 " .set noat \n" \
1298 " move $1, %0 \n" \
1299 " # mtlo $1, $ac1 \n" \
1300 " .word 0x00200813 \n" \
1301 " .set pop \n" \
1302 : \
1303 : "r" (x)); \
1304 } while (0)
1305
1306 #define mtlo2(x) \
1307 do { \
1308 __asm__ __volatile__( \
1309 " .set push \n" \
1310 " .set noat \n" \
1311 " move $1, %0 \n" \
1312 " # mtlo $1, $ac2 \n" \
1313 " .word 0x00201013 \n" \
1314 " .set pop \n" \
1315 : \
1316 : "r" (x)); \
1317 } while (0)
1318
1319 #define mtlo3(x) \
1320 do { \
1321 __asm__ __volatile__( \
1322 " .set push \n" \
1323 " .set noat \n" \
1324 " move $1, %0 \n" \
1325 " # mtlo $1, $ac3 \n" \
1326 " .word 0x00201813 \n" \
1327 " .set pop \n" \
1328 : \
1329 : "r" (x)); \
1330 } while (0)
1331
1332 #endif
1333
1334 /*
1335 * TLB operations.
1336 *
1337 * It is responsibility of the caller to take care of any TLB hazards.
1338 */
1339 static inline void tlb_probe(void)
1340 {
1341 __asm__ __volatile__(
1342 ".set noreorder\n\t"
1343 "tlbp\n\t"
1344 ".set reorder");
1345 }
1346
1347 static inline void tlb_read(void)
1348 {
1349 __asm__ __volatile__(
1350 ".set noreorder\n\t"
1351 "tlbr\n\t"
1352 ".set reorder");
1353 }
1354
1355 static inline void tlb_write_indexed(void)
1356 {
1357 __asm__ __volatile__(
1358 ".set noreorder\n\t"
1359 "tlbwi\n\t"
1360 ".set reorder");
1361 }
1362
1363 static inline void tlb_write_random(void)
1364 {
1365 __asm__ __volatile__(
1366 ".set noreorder\n\t"
1367 "tlbwr\n\t"
1368 ".set reorder");
1369 }
1370
1371 /*
1372 * Manipulate bits in a c0 register.
1373 */
1374 #ifndef CONFIG_MIPS_MT_SMTC
1375 /*
1376 * SMTC Linux requires shutting-down microthread scheduling
1377 * during CP0 register read-modify-write sequences.
1378 */
1379 #define __BUILD_SET_C0(name) \
1380 static inline unsigned int \
1381 set_c0_##name(unsigned int set) \
1382 { \
1383 unsigned int res; \
1384 \
1385 res = read_c0_##name(); \
1386 res |= set; \
1387 write_c0_##name(res); \
1388 \
1389 return res; \
1390 } \
1391 \
1392 static inline unsigned int \
1393 clear_c0_##name(unsigned int clear) \
1394 { \
1395 unsigned int res; \
1396 \
1397 res = read_c0_##name(); \
1398 res &= ~clear; \
1399 write_c0_##name(res); \
1400 \
1401 return res; \
1402 } \
1403 \
1404 static inline unsigned int \
1405 change_c0_##name(unsigned int change, unsigned int new) \
1406 { \
1407 unsigned int res; \
1408 \
1409 res = read_c0_##name(); \
1410 res &= ~change; \
1411 res |= (new & change); \
1412 write_c0_##name(res); \
1413 \
1414 return res; \
1415 }
1416
1417 #else /* SMTC versions that manage MT scheduling */
1418
1419 #include <asm/interrupt.h>
1420
1421 /*
1422 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1423 * header file recursion.
1424 */
1425 static inline unsigned int __dmt(void)
1426 {
1427 int res;
1428
1429 __asm__ __volatile__(
1430 " .set push \n"
1431 " .set mips32r2 \n"
1432 " .set noat \n"
1433 " .word 0x41610BC1 # dmt $1 \n"
1434 " ehb \n"
1435 " move %0, $1 \n"
1436 " .set pop \n"
1437 : "=r" (res));
1438
1439 instruction_hazard();
1440
1441 return res;
1442 }
1443
1444 #define __VPECONTROL_TE_SHIFT 15
1445 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1446
1447 #define __EMT_ENABLE __VPECONTROL_TE
1448
1449 static inline void __emt(unsigned int previous)
1450 {
1451 if ((previous & __EMT_ENABLE))
1452 __asm__ __volatile__(
1453 " .set mips32r2 \n"
1454 " .word 0x41600be1 # emt \n"
1455 " ehb \n"
1456 " .set mips0 \n");
1457 }
1458
1459 static inline void __ehb(void)
1460 {
1461 __asm__ __volatile__(
1462 " ehb \n");
1463 }
1464
1465 /*
1466 * Note that local_irq_save/restore affect TC-specific IXMT state,
1467 * not Status.IE as in non-SMTC kernel.
1468 */
1469
1470 #define __BUILD_SET_C0(name) \
1471 static inline unsigned int \
1472 set_c0_##name(unsigned int set) \
1473 { \
1474 unsigned int res; \
1475 unsigned int omt; \
1476 unsigned int flags; \
1477 \
1478 local_irq_save(flags); \
1479 omt = __dmt(); \
1480 res = read_c0_##name(); \
1481 res |= set; \
1482 write_c0_##name(res); \
1483 __emt(omt); \
1484 local_irq_restore(flags); \
1485 \
1486 return res; \
1487 } \
1488 \
1489 static inline unsigned int \
1490 clear_c0_##name(unsigned int clear) \
1491 { \
1492 unsigned int res; \
1493 unsigned int omt; \
1494 unsigned int flags; \
1495 \
1496 local_irq_save(flags); \
1497 omt = __dmt(); \
1498 res = read_c0_##name(); \
1499 res &= ~clear; \
1500 write_c0_##name(res); \
1501 __emt(omt); \
1502 local_irq_restore(flags); \
1503 \
1504 return res; \
1505 } \
1506 \
1507 static inline unsigned int \
1508 change_c0_##name(unsigned int change, unsigned int new) \
1509 { \
1510 unsigned int res; \
1511 unsigned int omt; \
1512 unsigned int flags; \
1513 \
1514 local_irq_save(flags); \
1515 \
1516 omt = __dmt(); \
1517 res = read_c0_##name(); \
1518 res &= ~change; \
1519 res |= (new & change); \
1520 write_c0_##name(res); \
1521 __emt(omt); \
1522 local_irq_restore(flags); \
1523 \
1524 return res; \
1525 }
1526 #endif
1527
1528 __BUILD_SET_C0(status)
1529 __BUILD_SET_C0(cause)
1530 __BUILD_SET_C0(config)
1531 __BUILD_SET_C0(intcontrol)
1532 __BUILD_SET_C0(intctl)
1533 __BUILD_SET_C0(srsmap)
1534
1535 #endif /* !__ASSEMBLY__ */
1536
1537 #endif /* _ASM_MIPSREGS_H */
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