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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - include/asm-mips/mmu_context.h
2 * Switch a MMU context.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 #ifndef _ASM_MMU_CONTEXT_H
12 #define _ASM_MMU_CONTEXT_H
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <asm/cacheflush.h>
18 #include <asm/tlbflush.h>
19 #ifdef CONFIG_MIPS_MT_SMTC
20 #include <asm/mipsmtregs.h>
23 #include <asm-generic/mm_hooks.h>
26 * For the fast tlb miss handlers, we keep a per cpu array of pointers
27 * to the current pgd for each processor. Also, the proc. id is stuffed
28 * into the context register.
30 extern unsigned long pgd_current
[];
32 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
33 pgd_current[smp_processor_id()] = (unsigned long)(pgd)
36 #define TLBMISS_HANDLER_SETUP() \
37 write_c0_context((unsigned long) smp_processor_id() << 25); \
38 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
41 #define TLBMISS_HANDLER_SETUP() \
42 write_c0_context((unsigned long) smp_processor_id() << 26); \
43 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
46 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
49 #define ASID_MASK 0xfc0
51 #elif defined(CONFIG_CPU_R8000)
54 #define ASID_MASK 0xff0
56 #elif defined(CONFIG_CPU_RM9000)
59 #define ASID_MASK 0xfff
61 /* SMTC/34K debug hack - but maybe we'll keep it */
62 #elif defined(CONFIG_MIPS_MT_SMTC)
65 extern unsigned long smtc_asid_mask
;
66 #define ASID_MASK (smtc_asid_mask)
67 #define HW_ASID_MASK 0xff
68 /* End SMTC/34K debug hack */
69 #else /* FIXME: not correct for R6000 */
72 #define ASID_MASK 0xff
76 #define cpu_context(cpu, mm) ((mm)->context[cpu])
77 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
78 #define asid_cache(cpu) (cpu_data[cpu].asid_cache)
80 static inline void enter_lazy_tlb(struct mm_struct
*mm
, struct task_struct
*tsk
)
85 * All unused by hardware upper bits will be considered
86 * as a software asid extension.
88 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
89 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
91 #ifndef CONFIG_MIPS_MT_SMTC
92 /* Normal, classic MIPS get_new_mmu_context */
94 get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
)
96 unsigned long asid
= asid_cache(cpu
);
98 if (! ((asid
+= ASID_INC
) & ASID_MASK
) ) {
99 if (cpu_has_vtag_icache
)
101 local_flush_tlb_all(); /* start new asid cycle */
102 if (!asid
) /* fix version if needed */
103 asid
= ASID_FIRST_VERSION
;
105 cpu_context(cpu
, mm
) = asid_cache(cpu
) = asid
;
108 #else /* CONFIG_MIPS_MT_SMTC */
110 #define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu))
112 #endif /* CONFIG_MIPS_MT_SMTC */
115 * Initialize the context related info for a new mm_struct
119 init_new_context(struct task_struct
*tsk
, struct mm_struct
*mm
)
123 for (i
= 0; i
< num_online_cpus(); i
++)
124 cpu_context(i
, mm
) = 0;
129 static inline void switch_mm(struct mm_struct
*prev
, struct mm_struct
*next
,
130 struct task_struct
*tsk
)
132 unsigned int cpu
= smp_processor_id();
134 #ifdef CONFIG_MIPS_MT_SMTC
135 unsigned long oldasid
;
136 unsigned long mtflags
;
137 int mytlb
= (smtc_status
& SMTC_TLB_SHARED
) ? 0 : cpu_data
[cpu
].vpe_id
;
138 local_irq_save(flags
);
141 local_irq_save(flags
);
142 #endif /* CONFIG_MIPS_MT_SMTC */
144 /* Check if our ASID is of an older version and thus invalid */
145 if ((cpu_context(cpu
, next
) ^ asid_cache(cpu
)) & ASID_VERSION_MASK
)
146 get_new_mmu_context(next
, cpu
);
147 #ifdef CONFIG_MIPS_MT_SMTC
149 * If the EntryHi ASID being replaced happens to be
150 * the value flagged at ASID recycling time as having
151 * an extended life, clear the bit showing it being
152 * in use by this "CPU", and if that's the last bit,
153 * free up the ASID value for use and flush any old
154 * instances of it from the TLB.
156 oldasid
= (read_c0_entryhi() & ASID_MASK
);
157 if(smtc_live_asid
[mytlb
][oldasid
]) {
158 smtc_live_asid
[mytlb
][oldasid
] &= ~(0x1 << cpu
);
159 if(smtc_live_asid
[mytlb
][oldasid
] == 0)
160 smtc_flush_tlb_asid(oldasid
);
163 * Tread softly on EntryHi, and so long as we support
164 * having ASID_MASK smaller than the hardware maximum,
165 * make sure no "soft" bits become "hard"...
167 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK
)
168 | (cpu_context(cpu
, next
) & ASID_MASK
));
169 ehb(); /* Make sure it propagates to TCStatus */
172 write_c0_entryhi(cpu_context(cpu
, next
));
173 #endif /* CONFIG_MIPS_MT_SMTC */
174 TLBMISS_HANDLER_SETUP_PGD(next
->pgd
);
177 * Mark current->active_mm as not "active" anymore.
178 * We don't want to mislead possible IPI tlb flush routines.
180 cpu_clear(cpu
, prev
->cpu_vm_mask
);
181 cpu_set(cpu
, next
->cpu_vm_mask
);
183 local_irq_restore(flags
);
187 * Destroy context related info for an mm_struct that is about
190 static inline void destroy_context(struct mm_struct
*mm
)
194 #define deactivate_mm(tsk,mm) do { } while (0)
197 * After we have set current->mm to a new value, this activates
198 * the context for the new mm so we see the new mappings.
201 activate_mm(struct mm_struct
*prev
, struct mm_struct
*next
)
204 unsigned int cpu
= smp_processor_id();
206 #ifdef CONFIG_MIPS_MT_SMTC
207 unsigned long oldasid
;
208 unsigned long mtflags
;
209 int mytlb
= (smtc_status
& SMTC_TLB_SHARED
) ? 0 : cpu_data
[cpu
].vpe_id
;
210 #endif /* CONFIG_MIPS_MT_SMTC */
212 local_irq_save(flags
);
214 /* Unconditionally get a new ASID. */
215 get_new_mmu_context(next
, cpu
);
217 #ifdef CONFIG_MIPS_MT_SMTC
218 /* See comments for similar code above */
220 oldasid
= read_c0_entryhi() & ASID_MASK
;
221 if(smtc_live_asid
[mytlb
][oldasid
]) {
222 smtc_live_asid
[mytlb
][oldasid
] &= ~(0x1 << cpu
);
223 if(smtc_live_asid
[mytlb
][oldasid
] == 0)
224 smtc_flush_tlb_asid(oldasid
);
226 /* See comments for similar code above */
227 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK
) |
228 (cpu_context(cpu
, next
) & ASID_MASK
));
229 ehb(); /* Make sure it propagates to TCStatus */
232 write_c0_entryhi(cpu_context(cpu
, next
));
233 #endif /* CONFIG_MIPS_MT_SMTC */
234 TLBMISS_HANDLER_SETUP_PGD(next
->pgd
);
236 /* mark mmu ownership change */
237 cpu_clear(cpu
, prev
->cpu_vm_mask
);
238 cpu_set(cpu
, next
->cpu_vm_mask
);
240 local_irq_restore(flags
);
244 * If mm is currently active_mm, we can't really drop it. Instead,
245 * we will get a new one for it.
248 drop_mmu_context(struct mm_struct
*mm
, unsigned cpu
)
251 #ifdef CONFIG_MIPS_MT_SMTC
252 unsigned long oldasid
;
253 /* Can't use spinlock because called from TLB flush within DVPE */
254 unsigned int prevvpe
;
255 int mytlb
= (smtc_status
& SMTC_TLB_SHARED
) ? 0 : cpu_data
[cpu
].vpe_id
;
256 #endif /* CONFIG_MIPS_MT_SMTC */
258 local_irq_save(flags
);
260 if (cpu_isset(cpu
, mm
->cpu_vm_mask
)) {
261 get_new_mmu_context(mm
, cpu
);
262 #ifdef CONFIG_MIPS_MT_SMTC
263 /* See comments for similar code above */
265 oldasid
= (read_c0_entryhi() & ASID_MASK
);
266 if (smtc_live_asid
[mytlb
][oldasid
]) {
267 smtc_live_asid
[mytlb
][oldasid
] &= ~(0x1 << cpu
);
268 if(smtc_live_asid
[mytlb
][oldasid
] == 0)
269 smtc_flush_tlb_asid(oldasid
);
271 /* See comments for similar code above */
272 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK
)
273 | cpu_asid(cpu
, mm
));
274 ehb(); /* Make sure it propagates to TCStatus */
276 #else /* not CONFIG_MIPS_MT_SMTC */
277 write_c0_entryhi(cpu_asid(cpu
, mm
));
278 #endif /* CONFIG_MIPS_MT_SMTC */
280 /* will get a new context next time */
281 #ifndef CONFIG_MIPS_MT_SMTC
282 cpu_context(cpu
, mm
) = 0;
286 /* SMTC shares the TLB (and ASIDs) across VPEs */
287 for (i
= 0; i
< num_online_cpus(); i
++) {
288 if((smtc_status
& SMTC_TLB_SHARED
)
289 || (cpu_data
[i
].vpe_id
== cpu_data
[cpu
].vpe_id
))
290 cpu_context(i
, mm
) = 0;
292 #endif /* CONFIG_MIPS_MT_SMTC */
294 local_irq_restore(flags
);
297 #endif /* _ASM_MMU_CONTEXT_H */