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2 * SNI specific definitions
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1997, 1998 by Ralf Baechle
9 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
14 extern unsigned int sni_brd_type
;
17 #define SNI_BRD_10NEW 3
18 #define SNI_BRD_TOWER_OASIC 4
19 #define SNI_BRD_MINITOWER 5
20 #define SNI_BRD_PCI_TOWER 6
21 #define SNI_BRD_RM200 7
22 #define SNI_BRD_PCI_MTOWER 8
23 #define SNI_BRD_PCI_DESKTOP 9
24 #define SNI_BRD_PCI_TOWER_CPLUS 10
25 #define SNI_BRD_PCI_MTOWER_CPLUS 11
28 #define SNI_CPU_M8021 0x01
29 #define SNI_CPU_M8030 0x04
30 #define SNI_CPU_M8031 0x06
31 #define SNI_CPU_M8034 0x0f
32 #define SNI_CPU_M8037 0x07
33 #define SNI_CPU_M8040 0x05
34 #define SNI_CPU_M8043 0x09
35 #define SNI_CPU_M8050 0x0b
36 #define SNI_CPU_M8053 0x0d
38 #define SNI_PORT_BASE 0xb4000000
42 * ASIC PCI registers for big endian configuration.
44 #define PCIMT_UCONF 0xbfff0004
45 #define PCIMT_IOADTIMEOUT2 0xbfff000c
46 #define PCIMT_IOMEMCONF 0xbfff0014
47 #define PCIMT_IOMMU 0xbfff001c
48 #define PCIMT_IOADTIMEOUT1 0xbfff0024
49 #define PCIMT_DMAACCESS 0xbfff002c
50 #define PCIMT_DMAHIT 0xbfff0034
51 #define PCIMT_ERRSTATUS 0xbfff003c
52 #define PCIMT_ERRADDR 0xbfff0044
53 #define PCIMT_SYNDROME 0xbfff004c
54 #define PCIMT_ITPEND 0xbfff0054
63 #define PCIMT_IRQSEL 0xbfff005c
64 #define PCIMT_TESTMEM 0xbfff0064
65 #define PCIMT_ECCREG 0xbfff006c
66 #define PCIMT_CONFIG_ADDRESS 0xbfff0074
67 #define PCIMT_ASIC_ID 0xbfff007c /* read */
68 #define PCIMT_SOFT_RESET 0xbfff007c /* write */
69 #define PCIMT_PIA_OE 0xbfff0084
70 #define PCIMT_PIA_DATAOUT 0xbfff008c
71 #define PCIMT_PIA_DATAIN 0xbfff0094
72 #define PCIMT_CACHECONF 0xbfff009c
73 #define PCIMT_INVSPACE 0xbfff00a4
76 * ASIC PCI registers for little endian configuration.
78 #define PCIMT_UCONF 0xbfff0000
79 #define PCIMT_IOADTIMEOUT2 0xbfff0008
80 #define PCIMT_IOMEMCONF 0xbfff0010
81 #define PCIMT_IOMMU 0xbfff0018
82 #define PCIMT_IOADTIMEOUT1 0xbfff0020
83 #define PCIMT_DMAACCESS 0xbfff0028
84 #define PCIMT_DMAHIT 0xbfff0030
85 #define PCIMT_ERRSTATUS 0xbfff0038
86 #define PCIMT_ERRADDR 0xbfff0040
87 #define PCIMT_SYNDROME 0xbfff0048
88 #define PCIMT_ITPEND 0xbfff0050
97 #define PCIMT_IRQSEL 0xbfff0058
98 #define PCIMT_TESTMEM 0xbfff0060
99 #define PCIMT_ECCREG 0xbfff0068
100 #define PCIMT_CONFIG_ADDRESS 0xbfff0070
101 #define PCIMT_ASIC_ID 0xbfff0078 /* read */
102 #define PCIMT_SOFT_RESET 0xbfff0078 /* write */
103 #define PCIMT_PIA_OE 0xbfff0080
104 #define PCIMT_PIA_DATAOUT 0xbfff0088
105 #define PCIMT_PIA_DATAIN 0xbfff0090
106 #define PCIMT_CACHECONF 0xbfff0098
107 #define PCIMT_INVSPACE 0xbfff00a0
110 #define PCIMT_PCI_CONF 0xbfff0100
113 * Data port for the PCI bus in IO space
115 #define PCIMT_CONFIG_DATA 0x0cfc
118 * Board specific registers
120 #define PCIMT_CSMSR 0xbfd00000
121 #define PCIMT_CSSWITCH 0xbfd10000
122 #define PCIMT_CSITPEND 0xbfd20000
123 #define PCIMT_AUTO_PO_EN 0xbfd30000
124 #define PCIMT_CLR_TEMP 0xbfd40000
125 #define PCIMT_AUTO_PO_DIS 0xbfd50000
126 #define PCIMT_EXMSR 0xbfd60000
127 #define PCIMT_UNUSED1 0xbfd70000
128 #define PCIMT_CSWCSM 0xbfd80000
129 #define PCIMT_UNUSED2 0xbfd90000
130 #define PCIMT_CSLED 0xbfda0000
131 #define PCIMT_CSMAPISA 0xbfdb0000
132 #define PCIMT_CSRSTBP 0xbfdc0000
133 #define PCIMT_CLRPOFF 0xbfdd0000
134 #define PCIMT_CSTIMER 0xbfde0000
135 #define PCIMT_PWDN 0xbfdf0000
140 #define A20R_PT_CLOCK_BASE 0xbc040000
141 #define A20R_PT_TIM0_ACK 0xbc050000
142 #define A20R_PT_TIM1_ACK 0xbc060000
144 #define SNI_MIPS_IRQ_CPU_TIMER (MIPS_CPU_IRQ_BASE+7)
146 #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
147 #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
149 #define SNI_PCIT_INT_REG 0xbfff000c
151 #define SNI_PCIT_INT_START 24
152 #define SNI_PCIT_INT_END 30
154 #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
155 #define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
156 #define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
157 #define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
158 #define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3)
159 #define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4)
160 #define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5)
164 * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
165 * to the other interrupts generated by ASIC PCI.
167 * INT2 is a wired-or of the push button interrupt, high temperature interrupt
168 * ASIC PCI interrupt.
170 #define PCIMT_KEYBOARD_IRQ 1
171 #define PCIMT_IRQ_INT2 24
172 #define PCIMT_IRQ_INTD 25
173 #define PCIMT_IRQ_INTC 26
174 #define PCIMT_IRQ_INTB 27
175 #define PCIMT_IRQ_INTA 28
176 #define PCIMT_IRQ_EISA 29
177 #define PCIMT_IRQ_SCSI 30
179 #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
182 #define PCIMT_IRQ_TEMPERATURE 24
183 #define PCIMT_IRQ_EISA_NMI 25
184 #define PCIMT_IRQ_POWER_OFF 26
185 #define PCIMT_IRQ_BUTTON 27
189 * Base address for the mapped 16mb EISA bus segment.
191 #define PCIMT_EISA_BASE 0xb0000000
193 /* PCI EISA Interrupt acknowledge */
194 #define PCIMT_INT_ACKNOWLEDGE 0xba000000
196 /* board specific init functions */
197 extern void sni_a20r_init (void);
198 extern void sni_pcit_init (void);
199 extern void sni_rm200_init (void);
200 extern void sni_pcimt_init (void);
202 /* board specific irq init functions */
203 extern void sni_a20r_irq_init (void);
204 extern void sni_pcit_irq_init (void);
205 extern void sni_pcit_cplus_irq_init (void);
206 extern void sni_rm200_irq_init (void);
207 extern void sni_pcimt_irq_init (void);
210 extern void sni_cpu_time_init(void);
212 /* common irq stuff */
213 extern void (*sni_hwint
)(void);
214 extern struct irqaction sni_isa_irq
;
216 #endif /* __ASM_SNI_H */