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2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc.
15 #include <linux/types.h>
16 #include <linux/irqflags.h>
18 #include <asm/addrspace.h>
19 #include <asm/barrier.h>
20 #include <asm/cpu-features.h>
26 * switch_to(n) should switch tasks to task nr n, first
27 * checking that n isn't the current task, in which case it does nothing.
29 extern asmlinkage
void *resume(void *last
, void *next
, void *next_ti
);
33 #ifdef CONFIG_MIPS_MT_FPAFF
36 * Handle the scheduler resume end of FPU affinity management. We do this
37 * inline to try to keep the overhead down. If we have been forced to run on
38 * a "CPU" with an FPU because of a previous high level of FP computation,
39 * but did not actually use the FPU during the most recent time-slice (CU1
40 * isn't set), we undo the restriction on cpus_allowed.
42 * We're not calling set_cpus_allowed() here, because we have no need to
43 * force prompt migration - we're already switching the current CPU to a
47 #define __mips_mt_fpaff_switch_to(prev) \
49 struct thread_info *__prev_ti = task_thread_info(prev); \
52 test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
53 (!(KSTK_STATUS(prev) & ST0_CU1))) { \
54 clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
55 prev->cpus_allowed = prev->thread.user_cpus_allowed; \
57 next->thread.emulated_fp = 0; \
61 #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
64 #define switch_to(prev,next,last) \
66 __mips_mt_fpaff_switch_to(prev); \
69 (last) = resume(prev, next, task_thread_info(next)); \
71 __restore_dsp(current); \
72 if (cpu_has_userlocal) \
73 write_c0_userlocal(task_thread_info(current)->tp_value);\
76 static inline unsigned long __xchg_u32(volatile int * m
, unsigned int val
)
80 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
85 "1: ll %0, %3 # xchg_u32 \n"
92 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
93 : "R" (*m
), "Jr" (val
)
95 } else if (cpu_has_llsc
) {
100 "1: ll %0, %3 # xchg_u32 \n"
110 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
111 : "R" (*m
), "Jr" (val
)
116 raw_local_irq_save(flags
);
119 raw_local_irq_restore(flags
); /* implies memory barrier */
128 static inline __u64
__xchg_u64(volatile __u64
* m
, __u64 val
)
132 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
135 __asm__
__volatile__(
137 "1: lld %0, %3 # xchg_u64 \n"
142 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
143 : "R" (*m
), "Jr" (val
)
145 } else if (cpu_has_llsc
) {
148 __asm__
__volatile__(
150 "1: lld %0, %3 # xchg_u64 \n"
158 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
159 : "R" (*m
), "Jr" (val
)
164 raw_local_irq_save(flags
);
167 raw_local_irq_restore(flags
); /* implies memory barrier */
175 extern __u64
__xchg_u64_unsupported_on_32bit_kernels(volatile __u64
* m
, __u64 val
);
176 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
179 /* This function doesn't exist, so you'll get a linker error
180 if something tries to do an invalid xchg(). */
181 extern void __xchg_called_with_bad_pointer(void);
183 static inline unsigned long __xchg(unsigned long x
, volatile void * ptr
, int size
)
187 return __xchg_u32(ptr
, x
);
189 return __xchg_u64(ptr
, x
);
191 __xchg_called_with_bad_pointer();
195 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
197 #define __HAVE_ARCH_CMPXCHG 1
199 static inline unsigned long __cmpxchg_u32(volatile int * m
, unsigned long old
,
204 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
205 __asm__
__volatile__(
209 "1: ll %0, %2 # __cmpxchg_u32 \n"
210 " bne %0, %z3, 2f \n"
218 : "=&r" (retval
), "=R" (*m
)
219 : "R" (*m
), "Jr" (old
), "Jr" (new)
221 } else if (cpu_has_llsc
) {
222 __asm__
__volatile__(
226 "1: ll %0, %2 # __cmpxchg_u32 \n"
227 " bne %0, %z3, 2f \n"
238 : "=&r" (retval
), "=R" (*m
)
239 : "R" (*m
), "Jr" (old
), "Jr" (new)
244 raw_local_irq_save(flags
);
248 raw_local_irq_restore(flags
); /* implies memory barrier */
256 static inline unsigned long __cmpxchg_u32_local(volatile int * m
,
257 unsigned long old
, unsigned long new)
261 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
262 __asm__
__volatile__(
266 "1: ll %0, %2 # __cmpxchg_u32 \n"
267 " bne %0, %z3, 2f \n"
275 : "=&r" (retval
), "=R" (*m
)
276 : "R" (*m
), "Jr" (old
), "Jr" (new)
278 } else if (cpu_has_llsc
) {
279 __asm__
__volatile__(
283 "1: ll %0, %2 # __cmpxchg_u32 \n"
284 " bne %0, %z3, 2f \n"
292 : "=&r" (retval
), "=R" (*m
)
293 : "R" (*m
), "Jr" (old
), "Jr" (new)
298 local_irq_save(flags
);
302 local_irq_restore(flags
); /* implies memory barrier */
309 static inline unsigned long __cmpxchg_u64(volatile int * m
, unsigned long old
,
314 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
315 __asm__
__volatile__(
319 "1: lld %0, %2 # __cmpxchg_u64 \n"
320 " bne %0, %z3, 2f \n"
326 : "=&r" (retval
), "=R" (*m
)
327 : "R" (*m
), "Jr" (old
), "Jr" (new)
329 } else if (cpu_has_llsc
) {
330 __asm__
__volatile__(
334 "1: lld %0, %2 # __cmpxchg_u64 \n"
335 " bne %0, %z3, 2f \n"
344 : "=&r" (retval
), "=R" (*m
)
345 : "R" (*m
), "Jr" (old
), "Jr" (new)
350 raw_local_irq_save(flags
);
354 raw_local_irq_restore(flags
); /* implies memory barrier */
362 static inline unsigned long __cmpxchg_u64_local(volatile int * m
,
363 unsigned long old
, unsigned long new)
367 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
368 __asm__
__volatile__(
372 "1: lld %0, %2 # __cmpxchg_u64 \n"
373 " bne %0, %z3, 2f \n"
379 : "=&r" (retval
), "=R" (*m
)
380 : "R" (*m
), "Jr" (old
), "Jr" (new)
382 } else if (cpu_has_llsc
) {
383 __asm__
__volatile__(
387 "1: lld %0, %2 # __cmpxchg_u64 \n"
388 " bne %0, %z3, 2f \n"
394 : "=&r" (retval
), "=R" (*m
)
395 : "R" (*m
), "Jr" (old
), "Jr" (new)
400 local_irq_save(flags
);
404 local_irq_restore(flags
); /* implies memory barrier */
411 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
412 volatile int * m
, unsigned long old
, unsigned long new);
413 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
414 extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels(
415 volatile int * m
, unsigned long old
, unsigned long new);
416 #define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels
419 /* This function doesn't exist, so you'll get a linker error
420 if something tries to do an invalid cmpxchg(). */
421 extern void __cmpxchg_called_with_bad_pointer(void);
423 static inline unsigned long __cmpxchg(volatile void * ptr
, unsigned long old
,
424 unsigned long new, int size
)
428 return __cmpxchg_u32(ptr
, old
, new);
430 return __cmpxchg_u64(ptr
, old
, new);
432 __cmpxchg_called_with_bad_pointer();
436 static inline unsigned long __cmpxchg_local(volatile void * ptr
,
437 unsigned long old
, unsigned long new, int size
)
441 return __cmpxchg_u32_local(ptr
, old
, new);
443 return __cmpxchg_u64_local(ptr
, old
, new);
445 __cmpxchg_called_with_bad_pointer();
449 #define cmpxchg(ptr,old,new) \
450 ((__typeof__(*(ptr)))__cmpxchg((ptr), \
451 (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
453 #define cmpxchg_local(ptr,old,new) \
454 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
455 (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
457 extern void set_handler (unsigned long offset
, void *addr
, unsigned long len
);
458 extern void set_uncached_handler (unsigned long offset
, void *addr
, unsigned long len
);
460 typedef void (*vi_handler_t
)(void);
461 extern void *set_vi_handler (int n
, vi_handler_t addr
);
463 extern void *set_except_vector(int n
, void *addr
);
464 extern unsigned long ebase
;
465 extern void per_cpu_trap_init(void);
467 extern int stop_a_enabled
;
470 * See include/asm-ia64/system.h; prevents deadlock on SMP
473 #define __ARCH_WANT_UNLOCKED_CTXSW
475 extern unsigned long arch_align_stack(unsigned long sp
);
477 #endif /* _ASM_SYSTEM_H */