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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - include/asm-mips/titan_dep.h
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
5 * Board specific definititions for the PMC-Sierra Yosemite
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef __TITAN_DEP_H__
14 #define __TITAN_DEP_H__
16 #include <asm/addrspace.h> /* for KSEG1ADDR() */
17 #include <asm/byteorder.h> /* for cpu_to_le32() */
19 #define TITAN_READ(ofs) \
20 (*(volatile u32 *)(ocd_base+(ofs)))
21 #define TITAN_READ_16(ofs) \
22 (*(volatile u16 *)(ocd_base+(ofs)))
23 #define TITAN_READ_8(ofs) \
24 (*(volatile u8 *)(ocd_base+(ofs)))
26 #define TITAN_WRITE(ofs, data) \
27 do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
28 #define TITAN_WRITE_16(ofs, data) \
29 do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
30 #define TITAN_WRITE_8(ofs, data) \
31 do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
34 * PCI specific defines
36 #define TITAN_PCI_0_CONFIG_ADDRESS 0x780
37 #define TITAN_PCI_0_CONFIG_DATA 0x784
42 #define RM9000x2_HTLINK_REG 0xbb000644
43 #define RM9000x2_BASE_ADDR 0xbb000000
45 #define OCD_BASE 0xfb000000UL
46 #define OCD_SIZE 0x3000UL
48 extern unsigned long ocd_base
;
53 #define RM9000x2_OCD_LKB5 0x0128 /* Ethernet */
54 #define RM9000x2_OCD_LKM5 0x012c
56 #define RM9000x2_OCD_LKB7 0x0138 /* HT Region 0 */
57 #define RM9000x2_OCD_LKM7 0x013c
58 #define RM9000x2_OCD_LKB8 0x0140 /* HT Region 1 */
59 #define RM9000x2_OCD_LKM8 0x0144
61 #define RM9000x2_OCD_LKB9 0x0148 /* Local Bus */
62 #define RM9000x2_OCD_LKM9 0x014c
63 #define RM9000x2_OCD_LKB10 0x0150
64 #define RM9000x2_OCD_LKM10 0x0154
65 #define RM9000x2_OCD_LKB11 0x0158
66 #define RM9000x2_OCD_LKM11 0x015c
67 #define RM9000x2_OCD_LKB12 0x0160
68 #define RM9000x2_OCD_LKM12 0x0164
70 #define RM9000x2_OCD_LKB13 0x0168 /* Scratch RAM */
71 #define RM9000x2_OCD_LKM13 0x016c
73 #define RM9000x2_OCD_LPD0 0x0200 /* Local Bus */
74 #define RM9000x2_OCD_LPD1 0x0210
75 #define RM9000x2_OCD_LPD2 0x0220
76 #define RM9000x2_OCD_LPD3 0x0230
78 #define RM9000x2_OCD_HTDVID 0x0600 /* HT Device Header */
79 #define RM9000x2_OCD_HTSC 0x0604
80 #define RM9000x2_OCD_HTCCR 0x0608
81 #define RM9000x2_OCD_HTBHL 0x060c
82 #define RM9000x2_OCD_HTBAR0 0x0610
83 #define RM9000x2_OCD_HTBAR1 0x0614
84 #define RM9000x2_OCD_HTBAR2 0x0618
85 #define RM9000x2_OCD_HTBAR3 0x061c
86 #define RM9000x2_OCD_HTBAR4 0x0620
87 #define RM9000x2_OCD_HTBAR5 0x0624
88 #define RM9000x2_OCD_HTCBCPT 0x0628
89 #define RM9000x2_OCD_HTSDVID 0x062c
90 #define RM9000x2_OCD_HTXRA 0x0630
91 #define RM9000x2_OCD_HTCAP1 0x0634
92 #define RM9000x2_OCD_HTIL 0x063c
94 #define RM9000x2_OCD_HTLCC 0x0640 /* HT Capability Block */
95 #define RM9000x2_OCD_HTLINK 0x0644
96 #define RM9000x2_OCD_HTFQREV 0x0648
98 #define RM9000x2_OCD_HTERCTL 0x0668 /* HT Controller */
99 #define RM9000x2_OCD_HTRXDB 0x066c
100 #define RM9000x2_OCD_HTIMPED 0x0670
101 #define RM9000x2_OCD_HTSWIMP 0x0674
102 #define RM9000x2_OCD_HTCAL 0x0678
104 #define RM9000x2_OCD_HTBAA30 0x0680
105 #define RM9000x2_OCD_HTBAA54 0x0684
106 #define RM9000x2_OCD_HTMASK0 0x0688
107 #define RM9000x2_OCD_HTMASK1 0x068c
108 #define RM9000x2_OCD_HTMASK2 0x0690
109 #define RM9000x2_OCD_HTMASK3 0x0694
110 #define RM9000x2_OCD_HTMASK4 0x0698
111 #define RM9000x2_OCD_HTMASK5 0x069c
113 #define RM9000x2_OCD_HTIFCTL 0x06a0
114 #define RM9000x2_OCD_HTPLL 0x06a4
116 #define RM9000x2_OCD_HTSRI 0x06b0
117 #define RM9000x2_OCD_HTRXNUM 0x06b4
118 #define RM9000x2_OCD_HTTXNUM 0x06b8
120 #define RM9000x2_OCD_HTTXCNT 0x06c8
122 #define RM9000x2_OCD_HTERROR 0x06d8
123 #define RM9000x2_OCD_HTRCRCE 0x06dc
124 #define RM9000x2_OCD_HTEOI 0x06e0
126 #define RM9000x2_OCD_CRCR 0x06f0
128 #define RM9000x2_OCD_HTCFGA 0x06f8
129 #define RM9000x2_OCD_HTCFGD 0x06fc
131 #define RM9000x2_OCD_INTMSG 0x0a00
133 #define RM9000x2_OCD_INTPIN0 0x0a40
134 #define RM9000x2_OCD_INTPIN1 0x0a44
135 #define RM9000x2_OCD_INTPIN2 0x0a48
136 #define RM9000x2_OCD_INTPIN3 0x0a4c
137 #define RM9000x2_OCD_INTPIN4 0x0a50
138 #define RM9000x2_OCD_INTPIN5 0x0a54
139 #define RM9000x2_OCD_INTPIN6 0x0a58
140 #define RM9000x2_OCD_INTPIN7 0x0a5c
141 #define RM9000x2_OCD_SEM 0x0a60
142 #define RM9000x2_OCD_SEMSET 0x0a64
143 #define RM9000x2_OCD_SEMCLR 0x0a68
145 #define RM9000x2_OCD_TKT 0x0a70
146 #define RM9000x2_OCD_TKTINC 0x0a74
148 #define RM9000x2_OCD_NMICONFIG 0x0ac0 /* Interrupts */
149 #define RM9000x2_OCD_INTP0PRI 0x1a80
150 #define RM9000x2_OCD_INTP1PRI 0x1a80
151 #define RM9000x2_OCD_INTP0STATUS0 0x1b00
152 #define RM9000x2_OCD_INTP0MASK0 0x1b04
153 #define RM9000x2_OCD_INTP0SET0 0x1b08
154 #define RM9000x2_OCD_INTP0CLEAR0 0x1b0c
155 #define RM9000x2_OCD_INTP0STATUS1 0x1b10
156 #define RM9000x2_OCD_INTP0MASK1 0x1b14
157 #define RM9000x2_OCD_INTP0SET1 0x1b18
158 #define RM9000x2_OCD_INTP0CLEAR1 0x1b1c
159 #define RM9000x2_OCD_INTP0STATUS2 0x1b20
160 #define RM9000x2_OCD_INTP0MASK2 0x1b24
161 #define RM9000x2_OCD_INTP0SET2 0x1b28
162 #define RM9000x2_OCD_INTP0CLEAR2 0x1b2c
163 #define RM9000x2_OCD_INTP0STATUS3 0x1b30
164 #define RM9000x2_OCD_INTP0MASK3 0x1b34
165 #define RM9000x2_OCD_INTP0SET3 0x1b38
166 #define RM9000x2_OCD_INTP0CLEAR3 0x1b3c
167 #define RM9000x2_OCD_INTP0STATUS4 0x1b40
168 #define RM9000x2_OCD_INTP0MASK4 0x1b44
169 #define RM9000x2_OCD_INTP0SET4 0x1b48
170 #define RM9000x2_OCD_INTP0CLEAR4 0x1b4c
171 #define RM9000x2_OCD_INTP0STATUS5 0x1b50
172 #define RM9000x2_OCD_INTP0MASK5 0x1b54
173 #define RM9000x2_OCD_INTP0SET5 0x1b58
174 #define RM9000x2_OCD_INTP0CLEAR5 0x1b5c
175 #define RM9000x2_OCD_INTP0STATUS6 0x1b60
176 #define RM9000x2_OCD_INTP0MASK6 0x1b64
177 #define RM9000x2_OCD_INTP0SET6 0x1b68
178 #define RM9000x2_OCD_INTP0CLEAR6 0x1b6c
179 #define RM9000x2_OCD_INTP0STATUS7 0x1b70
180 #define RM9000x2_OCD_INTP0MASK7 0x1b74
181 #define RM9000x2_OCD_INTP0SET7 0x1b78
182 #define RM9000x2_OCD_INTP0CLEAR7 0x1b7c
183 #define RM9000x2_OCD_INTP1STATUS0 0x2b00
184 #define RM9000x2_OCD_INTP1MASK0 0x2b04
185 #define RM9000x2_OCD_INTP1SET0 0x2b08
186 #define RM9000x2_OCD_INTP1CLEAR0 0x2b0c
187 #define RM9000x2_OCD_INTP1STATUS1 0x2b10
188 #define RM9000x2_OCD_INTP1MASK1 0x2b14
189 #define RM9000x2_OCD_INTP1SET1 0x2b18
190 #define RM9000x2_OCD_INTP1CLEAR1 0x2b1c
191 #define RM9000x2_OCD_INTP1STATUS2 0x2b20
192 #define RM9000x2_OCD_INTP1MASK2 0x2b24
193 #define RM9000x2_OCD_INTP1SET2 0x2b28
194 #define RM9000x2_OCD_INTP1CLEAR2 0x2b2c
195 #define RM9000x2_OCD_INTP1STATUS3 0x2b30
196 #define RM9000x2_OCD_INTP1MASK3 0x2b34
197 #define RM9000x2_OCD_INTP1SET3 0x2b38
198 #define RM9000x2_OCD_INTP1CLEAR3 0x2b3c
199 #define RM9000x2_OCD_INTP1STATUS4 0x2b40
200 #define RM9000x2_OCD_INTP1MASK4 0x2b44
201 #define RM9000x2_OCD_INTP1SET4 0x2b48
202 #define RM9000x2_OCD_INTP1CLEAR4 0x2b4c
203 #define RM9000x2_OCD_INTP1STATUS5 0x2b50
204 #define RM9000x2_OCD_INTP1MASK5 0x2b54
205 #define RM9000x2_OCD_INTP1SET5 0x2b58
206 #define RM9000x2_OCD_INTP1CLEAR5 0x2b5c
207 #define RM9000x2_OCD_INTP1STATUS6 0x2b60
208 #define RM9000x2_OCD_INTP1MASK6 0x2b64
209 #define RM9000x2_OCD_INTP1SET6 0x2b68
210 #define RM9000x2_OCD_INTP1CLEAR6 0x2b6c
211 #define RM9000x2_OCD_INTP1STATUS7 0x2b70
212 #define RM9000x2_OCD_INTP1MASK7 0x2b74
213 #define RM9000x2_OCD_INTP1SET7 0x2b78
214 #define RM9000x2_OCD_INTP1CLEAR7 0x2b7c
216 #define OCD_READ(reg) (*(volatile unsigned int *)(ocd_base + (reg)))
217 #define OCD_WRITE(reg, val) \
218 do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
221 * Hypertransport specific macros
223 #define RM9K_WRITE(ofs, data) *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
224 #define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
225 #define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
227 #define RM9K_READ(ofs, val) *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
228 #define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
229 #define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)