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2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
20 #include <asm/8xx_immap.h>
21 #include <asm/ptrace.h>
24 /* CPM Command register.
26 #define CPM_CR_RST ((ushort)0x8000)
27 #define CPM_CR_OPCODE ((ushort)0x0f00)
28 #define CPM_CR_CHAN ((ushort)0x00f0)
29 #define CPM_CR_FLG ((ushort)0x0001)
31 /* Some commands (there are more...later)
33 #define CPM_CR_INIT_TRX ((ushort)0x0000)
34 #define CPM_CR_INIT_RX ((ushort)0x0001)
35 #define CPM_CR_INIT_TX ((ushort)0x0002)
36 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
37 #define CPM_CR_STOP_TX ((ushort)0x0004)
38 #define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
39 #define CPM_CR_RESTART_TX ((ushort)0x0006)
40 #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
41 #define CPM_CR_SET_GADDR ((ushort)0x0008)
42 #define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
46 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
47 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
48 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
49 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
50 #define CPM_CR_CH_TIMER CPM_CR_CH_SPI
51 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
52 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
53 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
54 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
56 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
58 #ifndef CONFIG_PPC_CPM_NEW_BINDING
59 /* The dual ported RAM is multi-functional. Some areas can be (and are
60 * being) used for microcode. There is an area that can only be used
61 * as data ram for buffer descriptors, which is all we use right now.
62 * Currently the first 512 and last 256 bytes are used for microcode.
64 #define CPM_DATAONLY_BASE ((uint)0x0800)
65 #define CPM_DATAONLY_SIZE ((uint)0x0700)
66 #define CPM_DP_NOSPACE ((uint)0x7fffffff)
69 /* Export the base address of the communication processor registers
72 extern cpm8xx_t __iomem
*cpmp
; /* Pointer to comm processor */
74 #ifdef CONFIG_PPC_CPM_NEW_BINDING
75 #define cpm_dpalloc cpm_muram_alloc
76 #define cpm_dpfree cpm_muram_free
77 #define cpm_dpram_addr cpm_muram_addr
78 #define cpm_dpram_phys cpm_muram_dma
80 extern unsigned long cpm_dpalloc(uint size
, uint align
);
81 extern int cpm_dpfree(unsigned long offset
);
82 extern unsigned long cpm_dpalloc_fixed(unsigned long offset
, uint size
, uint align
);
83 extern void cpm_dpdump(void);
84 extern void *cpm_dpram_addr(unsigned long offset
);
85 extern uint
cpm_dpram_phys(u8
* addr
);
88 extern void cpm_setbrg(uint brg
, uint rate
);
90 extern uint
m8xx_cpm_hostalloc(uint size
);
91 extern int m8xx_cpm_hostfree(uint start
);
92 extern void m8xx_cpm_hostdump(void);
94 extern void cpm_load_patch(volatile immap_t
*immr
);
96 /* Buffer descriptors used by many of the CPM protocols.
98 typedef struct cpm_buf_desc
{
99 ushort cbd_sc
; /* Status and Control */
100 ushort cbd_datlen
; /* Data length in buffer */
101 uint cbd_bufaddr
; /* Buffer address in host memory */
104 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
105 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
106 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
107 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
108 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
109 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
110 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
111 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
112 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
113 #define BD_SC_BR ((ushort)0x0020) /* Break received */
114 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
115 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
116 #define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
117 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
118 #define BD_SC_UN ((ushort)0x0002) /* Underrun */
119 #define BD_SC_CD ((ushort)0x0001) /* ?? */
120 #define BD_SC_CL ((ushort)0x0001) /* Collision */
122 /* Parameter RAM offsets.
124 #define PROFF_SCC1 ((uint)0x0000)
125 #define PROFF_IIC ((uint)0x0080)
126 #define PROFF_SCC2 ((uint)0x0100)
127 #define PROFF_SPI ((uint)0x0180)
128 #define PROFF_SCC3 ((uint)0x0200)
129 #define PROFF_SMC1 ((uint)0x0280)
130 #define PROFF_SCC4 ((uint)0x0300)
131 #define PROFF_SMC2 ((uint)0x0380)
133 /* Define enough so I can at least use the serial port as a UART.
134 * The MBX uses SMC1 as the host serial port.
136 typedef struct smc_uart
{
137 ushort smc_rbase
; /* Rx Buffer descriptor base address */
138 ushort smc_tbase
; /* Tx Buffer descriptor base address */
139 u_char smc_rfcr
; /* Rx function code */
140 u_char smc_tfcr
; /* Tx function code */
141 ushort smc_mrblr
; /* Max receive buffer length */
142 uint smc_rstate
; /* Internal */
143 uint smc_idp
; /* Internal */
144 ushort smc_rbptr
; /* Internal */
145 ushort smc_ibc
; /* Internal */
146 uint smc_rxtmp
; /* Internal */
147 uint smc_tstate
; /* Internal */
148 uint smc_tdp
; /* Internal */
149 ushort smc_tbptr
; /* Internal */
150 ushort smc_tbc
; /* Internal */
151 uint smc_txtmp
; /* Internal */
152 ushort smc_maxidl
; /* Maximum idle characters */
153 ushort smc_tmpidl
; /* Temporary idle counter */
154 ushort smc_brklen
; /* Last received break length */
155 ushort smc_brkec
; /* rcv'd break condition counter */
156 ushort smc_brkcr
; /* xmt break count register */
157 ushort smc_rmask
; /* Temporary bit mask */
158 char res1
[8]; /* Reserved */
159 ushort smc_rpbase
; /* Relocation pointer */
162 /* Function code bits.
164 #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
166 /* SMC uart mode register.
168 #define SMCMR_REN ((ushort)0x0001)
169 #define SMCMR_TEN ((ushort)0x0002)
170 #define SMCMR_DM ((ushort)0x000c)
171 #define SMCMR_SM_GCI ((ushort)0x0000)
172 #define SMCMR_SM_UART ((ushort)0x0020)
173 #define SMCMR_SM_TRANS ((ushort)0x0030)
174 #define SMCMR_SM_MASK ((ushort)0x0030)
175 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
176 #define SMCMR_REVD SMCMR_PM_EVEN
177 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
178 #define SMCMR_BS SMCMR_PEN
179 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
180 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
181 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
183 /* SMC2 as Centronics parallel printer. It is half duplex, in that
184 * it can only receive or transmit. The parameter ram values for
185 * each direction are either unique or properly overlap, so we can
186 * include them in one structure.
188 typedef struct smc_centronics
{
206 ushort scent_character1
;
207 ushort scent_character2
;
208 ushort scent_character3
;
209 ushort scent_character4
;
210 ushort scent_character5
;
211 ushort scent_character6
;
212 ushort scent_character7
;
213 ushort scent_character8
;
218 /* Centronics Status Mask Register.
220 #define SMC_CENT_F ((u_char)0x08)
221 #define SMC_CENT_PE ((u_char)0x04)
222 #define SMC_CENT_S ((u_char)0x02)
224 /* SMC Event and Mask register.
226 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
227 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
228 #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
229 #define SMCM_BSY ((unsigned char)0x04)
230 #define SMCM_TX ((unsigned char)0x02)
231 #define SMCM_RX ((unsigned char)0x01)
233 /* Baud rate generators.
235 #define CPM_BRG_RST ((uint)0x00020000)
236 #define CPM_BRG_EN ((uint)0x00010000)
237 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
238 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
239 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
240 #define CPM_BRG_ATB ((uint)0x00002000)
241 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
242 #define CPM_BRG_DIV16 ((uint)0x00000001)
244 /* SI Clock Route Register
246 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
247 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
248 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
249 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
250 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
251 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
252 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
253 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
257 #define SCC_GSMRH_IRP ((uint)0x00040000)
258 #define SCC_GSMRH_GDE ((uint)0x00010000)
259 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
260 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
261 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
262 #define SCC_GSMRH_REVD ((uint)0x00002000)
263 #define SCC_GSMRH_TRX ((uint)0x00001000)
264 #define SCC_GSMRH_TTX ((uint)0x00000800)
265 #define SCC_GSMRH_CDP ((uint)0x00000400)
266 #define SCC_GSMRH_CTSP ((uint)0x00000200)
267 #define SCC_GSMRH_CDS ((uint)0x00000100)
268 #define SCC_GSMRH_CTSS ((uint)0x00000080)
269 #define SCC_GSMRH_TFL ((uint)0x00000040)
270 #define SCC_GSMRH_RFW ((uint)0x00000020)
271 #define SCC_GSMRH_TXSY ((uint)0x00000010)
272 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
273 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
274 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
275 #define SCC_GSMRH_RTSM ((uint)0x00000002)
276 #define SCC_GSMRH_RSYN ((uint)0x00000001)
278 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
279 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
280 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
281 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
282 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
283 #define SCC_GSMRL_TCI ((uint)0x10000000)
284 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
285 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
286 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
287 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
288 #define SCC_GSMRL_RINV ((uint)0x02000000)
289 #define SCC_GSMRL_TINV ((uint)0x01000000)
290 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
291 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
292 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
293 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
294 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
295 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
296 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
297 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
298 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
299 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
300 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
301 #define SCC_GSMRL_TEND ((uint)0x00040000)
302 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
303 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
304 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
305 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
306 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
307 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
308 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
309 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
310 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
311 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
312 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
313 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
314 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
315 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
316 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
317 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
318 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
319 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
320 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
321 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
322 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
323 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
324 #define SCC_GSMRL_ENR ((uint)0x00000020)
325 #define SCC_GSMRL_ENT ((uint)0x00000010)
326 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
327 #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
328 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
329 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
330 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
331 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
332 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
333 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
334 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
335 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
336 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
338 #define SCC_TODR_TOD ((ushort)0x8000)
340 /* SCC Event and Mask register.
342 #define SCCM_TXE ((unsigned char)0x10)
343 #define SCCM_BSY ((unsigned char)0x04)
344 #define SCCM_TX ((unsigned char)0x02)
345 #define SCCM_RX ((unsigned char)0x01)
347 typedef struct scc_param
{
348 ushort scc_rbase
; /* Rx Buffer descriptor base address */
349 ushort scc_tbase
; /* Tx Buffer descriptor base address */
350 u_char scc_rfcr
; /* Rx function code */
351 u_char scc_tfcr
; /* Tx function code */
352 ushort scc_mrblr
; /* Max receive buffer length */
353 uint scc_rstate
; /* Internal */
354 uint scc_idp
; /* Internal */
355 ushort scc_rbptr
; /* Internal */
356 ushort scc_ibc
; /* Internal */
357 uint scc_rxtmp
; /* Internal */
358 uint scc_tstate
; /* Internal */
359 uint scc_tdp
; /* Internal */
360 ushort scc_tbptr
; /* Internal */
361 ushort scc_tbc
; /* Internal */
362 uint scc_txtmp
; /* Internal */
363 uint scc_rcrc
; /* Internal */
364 uint scc_tcrc
; /* Internal */
367 /* Function code bits.
369 #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
371 /* CPM Ethernet through SCCx.
373 typedef struct scc_enet
{
375 uint sen_cpres
; /* Preset CRC */
376 uint sen_cmask
; /* Constant mask for CRC */
377 uint sen_crcec
; /* CRC Error counter */
378 uint sen_alec
; /* alignment error counter */
379 uint sen_disfc
; /* discard frame counter */
380 ushort sen_pads
; /* Tx short frame pad character */
381 ushort sen_retlim
; /* Retry limit threshold */
382 ushort sen_retcnt
; /* Retry limit counter */
383 ushort sen_maxflr
; /* maximum frame length register */
384 ushort sen_minflr
; /* minimum frame length register */
385 ushort sen_maxd1
; /* maximum DMA1 length */
386 ushort sen_maxd2
; /* maximum DMA2 length */
387 ushort sen_maxd
; /* Rx max DMA */
388 ushort sen_dmacnt
; /* Rx DMA counter */
389 ushort sen_maxb
; /* Max BD byte count */
390 ushort sen_gaddr1
; /* Group address filter */
394 uint sen_tbuf0data0
; /* Save area 0 - current frame */
395 uint sen_tbuf0data1
; /* Save area 1 - current frame */
396 uint sen_tbuf0rba
; /* Internal */
397 uint sen_tbuf0crc
; /* Internal */
398 ushort sen_tbuf0bcnt
; /* Internal */
399 ushort sen_paddrh
; /* physical address (MSB) */
401 ushort sen_paddrl
; /* physical address (LSB) */
402 ushort sen_pper
; /* persistence */
403 ushort sen_rfbdptr
; /* Rx first BD pointer */
404 ushort sen_tfbdptr
; /* Tx first BD pointer */
405 ushort sen_tlbdptr
; /* Tx last BD pointer */
406 uint sen_tbuf1data0
; /* Save area 0 - current frame */
407 uint sen_tbuf1data1
; /* Save area 1 - current frame */
408 uint sen_tbuf1rba
; /* Internal */
409 uint sen_tbuf1crc
; /* Internal */
410 ushort sen_tbuf1bcnt
; /* Internal */
411 ushort sen_txlen
; /* Tx Frame length counter */
412 ushort sen_iaddr1
; /* Individual address filter */
416 ushort sen_boffcnt
; /* Backoff counter */
418 /* NOTE: Some versions of the manual have the following items
419 * incorrectly documented. Below is the proper order.
421 ushort sen_taddrh
; /* temp address (MSB) */
423 ushort sen_taddrl
; /* temp address (LSB) */
426 /* SCC Event register as used by Ethernet.
428 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
429 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
430 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
431 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
432 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
433 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
435 /* SCC Mode Register (PMSR) as used by Ethernet.
437 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
438 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
439 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
440 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
441 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
442 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
443 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
444 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
445 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
446 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
447 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
448 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
449 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
451 /* Buffer descriptor control/status used by Ethernet receive.
453 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
454 #define BD_ENET_RX_WRAP ((ushort)0x2000)
455 #define BD_ENET_RX_INTR ((ushort)0x1000)
456 #define BD_ENET_RX_LAST ((ushort)0x0800)
457 #define BD_ENET_RX_FIRST ((ushort)0x0400)
458 #define BD_ENET_RX_MISS ((ushort)0x0100)
459 #define BD_ENET_RX_LG ((ushort)0x0020)
460 #define BD_ENET_RX_NO ((ushort)0x0010)
461 #define BD_ENET_RX_SH ((ushort)0x0008)
462 #define BD_ENET_RX_CR ((ushort)0x0004)
463 #define BD_ENET_RX_OV ((ushort)0x0002)
464 #define BD_ENET_RX_CL ((ushort)0x0001)
465 #define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */
466 #define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */
467 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
469 /* Buffer descriptor control/status used by Ethernet transmit.
471 #define BD_ENET_TX_READY ((ushort)0x8000)
472 #define BD_ENET_TX_PAD ((ushort)0x4000)
473 #define BD_ENET_TX_WRAP ((ushort)0x2000)
474 #define BD_ENET_TX_INTR ((ushort)0x1000)
475 #define BD_ENET_TX_LAST ((ushort)0x0800)
476 #define BD_ENET_TX_TC ((ushort)0x0400)
477 #define BD_ENET_TX_DEF ((ushort)0x0200)
478 #define BD_ENET_TX_HB ((ushort)0x0100)
479 #define BD_ENET_TX_LC ((ushort)0x0080)
480 #define BD_ENET_TX_RL ((ushort)0x0040)
481 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
482 #define BD_ENET_TX_UN ((ushort)0x0002)
483 #define BD_ENET_TX_CSL ((ushort)0x0001)
484 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
488 typedef struct scc_uart
{
490 char res1
[8]; /* Reserved */
491 ushort scc_maxidl
; /* Maximum idle chars */
492 ushort scc_idlc
; /* temp idle counter */
493 ushort scc_brkcr
; /* Break count register */
494 ushort scc_parec
; /* receive parity error counter */
495 ushort scc_frmec
; /* receive framing error counter */
496 ushort scc_nosec
; /* receive noise counter */
497 ushort scc_brkec
; /* receive break condition counter */
498 ushort scc_brkln
; /* last received break length */
499 ushort scc_uaddr1
; /* UART address character 1 */
500 ushort scc_uaddr2
; /* UART address character 2 */
501 ushort scc_rtemp
; /* Temp storage */
502 ushort scc_toseq
; /* Transmit out of sequence char */
503 ushort scc_char1
; /* control character 1 */
504 ushort scc_char2
; /* control character 2 */
505 ushort scc_char3
; /* control character 3 */
506 ushort scc_char4
; /* control character 4 */
507 ushort scc_char5
; /* control character 5 */
508 ushort scc_char6
; /* control character 6 */
509 ushort scc_char7
; /* control character 7 */
510 ushort scc_char8
; /* control character 8 */
511 ushort scc_rccm
; /* receive control character mask */
512 ushort scc_rccr
; /* receive control character register */
513 ushort scc_rlbc
; /* receive last break character */
516 /* SCC Event and Mask registers when it is used as a UART.
518 #define UART_SCCM_GLR ((ushort)0x1000)
519 #define UART_SCCM_GLT ((ushort)0x0800)
520 #define UART_SCCM_AB ((ushort)0x0200)
521 #define UART_SCCM_IDL ((ushort)0x0100)
522 #define UART_SCCM_GRA ((ushort)0x0080)
523 #define UART_SCCM_BRKE ((ushort)0x0040)
524 #define UART_SCCM_BRKS ((ushort)0x0020)
525 #define UART_SCCM_CCR ((ushort)0x0008)
526 #define UART_SCCM_BSY ((ushort)0x0004)
527 #define UART_SCCM_TX ((ushort)0x0002)
528 #define UART_SCCM_RX ((ushort)0x0001)
530 /* The SCC PMSR when used as a UART.
532 #define SCU_PSMR_FLC ((ushort)0x8000)
533 #define SCU_PSMR_SL ((ushort)0x4000)
534 #define SCU_PSMR_CL ((ushort)0x3000)
535 #define SCU_PSMR_UM ((ushort)0x0c00)
536 #define SCU_PSMR_FRZ ((ushort)0x0200)
537 #define SCU_PSMR_RZS ((ushort)0x0100)
538 #define SCU_PSMR_SYN ((ushort)0x0080)
539 #define SCU_PSMR_DRT ((ushort)0x0040)
540 #define SCU_PSMR_PEN ((ushort)0x0010)
541 #define SCU_PSMR_RPM ((ushort)0x000c)
542 #define SCU_PSMR_REVP ((ushort)0x0008)
543 #define SCU_PSMR_TPM ((ushort)0x0003)
544 #define SCU_PSMR_TEVP ((ushort)0x0002)
546 /* CPM Transparent mode SCC.
548 typedef struct scc_trans
{
550 uint st_cpres
; /* Preset CRC */
551 uint st_cmask
; /* Constant mask for CRC */
554 #define BD_SCC_TX_LAST ((ushort)0x0800)
556 /* IIC parameter RAM.
559 ushort iic_rbase
; /* Rx Buffer descriptor base address */
560 ushort iic_tbase
; /* Tx Buffer descriptor base address */
561 u_char iic_rfcr
; /* Rx function code */
562 u_char iic_tfcr
; /* Tx function code */
563 ushort iic_mrblr
; /* Max receive buffer length */
564 uint iic_rstate
; /* Internal */
565 uint iic_rdp
; /* Internal */
566 ushort iic_rbptr
; /* Internal */
567 ushort iic_rbc
; /* Internal */
568 uint iic_rxtmp
; /* Internal */
569 uint iic_tstate
; /* Internal */
570 uint iic_tdp
; /* Internal */
571 ushort iic_tbptr
; /* Internal */
572 ushort iic_tbc
; /* Internal */
573 uint iic_txtmp
; /* Internal */
574 char res1
[4]; /* Reserved */
575 ushort iic_rpbase
; /* Relocation pointer */
576 char res2
[2]; /* Reserved */
579 #define BD_IIC_START ((ushort)0x0400)
581 /* SPI parameter RAM.
584 ushort spi_rbase
; /* Rx Buffer descriptor base address */
585 ushort spi_tbase
; /* Tx Buffer descriptor base address */
586 u_char spi_rfcr
; /* Rx function code */
587 u_char spi_tfcr
; /* Tx function code */
588 ushort spi_mrblr
; /* Max receive buffer length */
589 uint spi_rstate
; /* Internal */
590 uint spi_rdp
; /* Internal */
591 ushort spi_rbptr
; /* Internal */
592 ushort spi_rbc
; /* Internal */
593 uint spi_rxtmp
; /* Internal */
594 uint spi_tstate
; /* Internal */
595 uint spi_tdp
; /* Internal */
596 ushort spi_tbptr
; /* Internal */
597 ushort spi_tbc
; /* Internal */
598 uint spi_txtmp
; /* Internal */
600 ushort spi_rpbase
; /* Relocation pointer */
604 /* SPI Mode register.
606 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
607 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
608 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
609 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
610 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
611 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
612 #define SPMODE_EN ((ushort)0x0100) /* Enable */
613 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
614 #define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
615 #define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
616 #define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
617 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
620 #define SPIE_MME 0x20
621 #define SPIE_TXE 0x10
622 #define SPIE_BSY 0x04
623 #define SPIE_TXB 0x02
624 #define SPIE_RXB 0x01
627 * RISC Controller Configuration Register definitons
629 #define RCCR_TIME 0x8000 /* RISC Timer Enable */
630 #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
631 #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
633 /* RISC Timer Parameter RAM offset */
634 #define PROFF_RTMR ((uint)0x01B0)
636 typedef struct risc_timer_pram
{
637 unsigned short tm_base
; /* RISC Timer Table Base Address */
638 unsigned short tm_ptr
; /* RISC Timer Table Pointer (internal) */
639 unsigned short r_tmr
; /* RISC Timer Mode Register */
640 unsigned short r_tmv
; /* RISC Timer Valid Register */
641 unsigned long tm_cmd
; /* RISC Timer Command Register */
642 unsigned long tm_cnt
; /* RISC Timer Internal Count */
645 /* Bits in RISC Timer Command Register */
646 #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
647 #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
648 #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
649 #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
650 #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
652 /* CPM interrupts. There are nearly 32 interrupts generated by CPM
653 * channels or devices. All of these are presented to the PPC core
654 * as a single interrupt. The CPM interrupt handler dispatches its
655 * own handlers, in a similar fashion to the PPC core handler. We
656 * use the table as defined in the manuals (i.e. no special high
657 * priority and SCC1 == SCCa, etc...).
660 #define CPMVEC_PIO_PC15 ((ushort)0x1f)
661 #define CPMVEC_SCC1 ((ushort)0x1e)
662 #define CPMVEC_SCC2 ((ushort)0x1d)
663 #define CPMVEC_SCC3 ((ushort)0x1c)
664 #define CPMVEC_SCC4 ((ushort)0x1b)
665 #define CPMVEC_PIO_PC14 ((ushort)0x1a)
666 #define CPMVEC_TIMER1 ((ushort)0x19)
667 #define CPMVEC_PIO_PC13 ((ushort)0x18)
668 #define CPMVEC_PIO_PC12 ((ushort)0x17)
669 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
670 #define CPMVEC_IDMA1 ((ushort)0x15)
671 #define CPMVEC_IDMA2 ((ushort)0x14)
672 #define CPMVEC_TIMER2 ((ushort)0x12)
673 #define CPMVEC_RISCTIMER ((ushort)0x11)
674 #define CPMVEC_I2C ((ushort)0x10)
675 #define CPMVEC_PIO_PC11 ((ushort)0x0f)
676 #define CPMVEC_PIO_PC10 ((ushort)0x0e)
677 #define CPMVEC_TIMER3 ((ushort)0x0c)
678 #define CPMVEC_PIO_PC9 ((ushort)0x0b)
679 #define CPMVEC_PIO_PC8 ((ushort)0x0a)
680 #define CPMVEC_PIO_PC7 ((ushort)0x09)
681 #define CPMVEC_TIMER4 ((ushort)0x07)
682 #define CPMVEC_PIO_PC6 ((ushort)0x06)
683 #define CPMVEC_SPI ((ushort)0x05)
684 #define CPMVEC_SMC1 ((ushort)0x04)
685 #define CPMVEC_SMC2 ((ushort)0x03)
686 #define CPMVEC_PIO_PC5 ((ushort)0x02)
687 #define CPMVEC_PIO_PC4 ((ushort)0x01)
688 #define CPMVEC_ERROR ((ushort)0x00)
690 /* CPM interrupt configuration vector.
692 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
693 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
694 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
695 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
696 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
697 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
698 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
699 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
701 extern void cpm_install_handler(int vec
, void (*handler
)(void *), void *dev_id
);
702 extern void cpm_free_handler(int vec
);
704 #define IMAP_ADDR (get_immrbase())
706 #define CPM_PIN_INPUT 0
707 #define CPM_PIN_OUTPUT 1
708 #define CPM_PIN_PRIMARY 0
709 #define CPM_PIN_SECONDARY 2
710 #define CPM_PIN_GPIO 4
711 #define CPM_PIN_OPENDRAIN 8
721 void cpm1_set_pin(enum cpm_port port
, int pin
, int flags
);
729 enum cpm_clk_target
{
739 CPM_BRG1
, /* Baud Rate Generator 1 */
740 CPM_BRG2
, /* Baud Rate Generator 2 */
741 CPM_BRG3
, /* Baud Rate Generator 3 */
742 CPM_BRG4
, /* Baud Rate Generator 4 */
743 CPM_CLK1
, /* Clock 1 */
744 CPM_CLK2
, /* Clock 2 */
745 CPM_CLK3
, /* Clock 3 */
746 CPM_CLK4
, /* Clock 4 */
747 CPM_CLK5
, /* Clock 5 */
748 CPM_CLK6
, /* Clock 6 */
749 CPM_CLK7
, /* Clock 7 */
750 CPM_CLK8
, /* Clock 8 */
753 int cpm1_clk_setup(enum cpm_clk_target target
, int clock
, int mode
);
755 #endif /* __CPM_8XX__ */