include/asm-powerpc/io.h

   1 #ifndef _ASM_POWERPC_IO_H
   2 #define _ASM_POWERPC_IO_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 /* Check of existence of legacy devices */
  13 extern int check_legacy_ioport(unsigned long base_port);
  14 #define PNPBIOS_BASE    0xf000  /* only relevant for PReP */
  15
  16 #ifndef CONFIG_PPC64
  17 #include <asm-ppc/io.h>
  18 #else
  19
  20 #include <linux/compiler.h>
  21 #include <asm/page.h>
  22 #include <asm/byteorder.h>
  23 #include <asm/paca.h>
  24 #include <asm/synch.h>
  25 #include <asm/delay.h>
  26
  27 #include <asm-generic/iomap.h>
  28
  29 #define SIO_CONFIG_RA   0x398
  30 #define SIO_CONFIG_RD   0x399
  31
  32 #define SLOW_DOWN_IO
  33
  34 /*
  35  *
  36  * Low level MMIO accessors
  37  *
  38  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  39  * specific and thus shouldn't be used in generic code. The accessors
  40  * provided here are:
  41  *
  42  *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  43  *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  44  *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  45  *
  46  * Those operate directly on a kernel virtual address. Note that the prototype
  47  * for the out_* accessors has the arguments in opposite order from the usual
  48  * linux PCI accessors. Unlike those, they take the address first and the value
  49  * next.
  50  *
  51  * Note: I might drop the _ns suffix on the stream operations soon as it is
  52  * simply normal for stream operations to not swap in the first place.
  53  *
  54  */
  55
  56 #define IO_SET_SYNC_FLAG()      do { get_paca()->io_sync = 1; } while(0)
  57
  58 #define DEF_MMIO_IN(name, type, insn)                                   \
  59 static inline type name(const volatile type __iomem *addr)              \
  60 {                                                                       \
  61         type ret;                                                       \
  62         __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync"           \
  63                 : "=r" (ret) : "r" (addr), "m" (*addr));                \
  64         return ret;                                                     \
  65 }
  66
  67 #define DEF_MMIO_OUT(name, type, insn)                                  \
  68 static inline void name(volatile type __iomem *addr, type val)          \
  69 {                                                                       \
  70         __asm__ __volatile__("sync;" insn                               \
  71                 : "=m" (*addr) : "r" (val), "r" (addr));                \
  72         IO_SET_SYNC_FLAG();                                     \
  73 }
  74
  75
  76 #define DEF_MMIO_IN_BE(name, size, insn) \
  77         DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2")
  78 #define DEF_MMIO_IN_LE(name, size, insn) \
  79         DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1")
  80
  81 #define DEF_MMIO_OUT_BE(name, size, insn) \
  82         DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0")
  83 #define DEF_MMIO_OUT_LE(name, size, insn) \
  84         DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2")
  85
  86 DEF_MMIO_IN_BE(in_8,     8, lbz);
  87 DEF_MMIO_IN_BE(in_be16, 16, lhz);
  88 DEF_MMIO_IN_BE(in_be32, 32, lwz);
  89 DEF_MMIO_IN_BE(in_be64, 64, ld);
  90 DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
  91 DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
  92
  93 DEF_MMIO_OUT_BE(out_8,     8, stb);
  94 DEF_MMIO_OUT_BE(out_be16, 16, sth);
  95 DEF_MMIO_OUT_BE(out_be32, 32, stw);
  96 DEF_MMIO_OUT_BE(out_be64, 64, std);
  97 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
  98 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
  99
 100 /* There is no asm instructions for 64 bits reverse loads and stores */
 101 static inline u64 in_le64(const volatile u64 __iomem *addr)
 102 {
 103         return le64_to_cpu(in_be64(addr));
 104 }
 105
 106 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
 107 {
 108         out_be64(addr, cpu_to_le64(val));
 109 }
 110
 111 /*
 112  * Low level IO stream instructions are defined out of line for now
 113  */
 114 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
 115 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
 116 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
 117 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
 118 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
 119 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 120
 121 /* The _ns naming is historical and will be removed. For now, just #define
 122  * the non _ns equivalent names
 123  */
 124 #define _insw   _insw_ns
 125 #define _insl   _insl_ns
 126 #define _outsw  _outsw_ns
 127 #define _outsl  _outsl_ns
 128
 129 /*
 130  *
 131  * PCI and standard ISA accessors
 132  *
 133  * Those are globally defined linux accessors for devices on PCI or ISA
 134  * busses. They follow the Linux defined semantics. The current implementation
 135  * for PowerPC is as close as possible to the x86 version of these, and thus
 136  * provides fairly heavy weight barriers for the non-raw versions
 137  *
 138  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
 139  * allowing the platform to provide its own implementation of some or all
 140  * of the accessors.
 141  */
 142
 143 extern unsigned long isa_io_base;
 144 extern unsigned long pci_io_base;
 145
 146
 147 /*
 148  * Non ordered and non-swapping "raw" accessors
 149  */
 150
 151 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 152 {
 153         return *(volatile unsigned char __force *)addr;
 154 }
 155 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 156 {
 157         return *(volatile unsigned short __force *)addr;
 158 }
 159 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 160 {
 161         return *(volatile unsigned int __force *)addr;
 162 }
 163 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
 164 {
 165         return *(volatile unsigned long __force *)addr;
 166 }
 167 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 168 {
 169         *(volatile unsigned char __force *)addr = v;
 170 }
 171 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 172 {
 173         *(volatile unsigned short __force *)addr = v;
 174 }
 175 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 176 {
 177         *(volatile unsigned int __force *)addr = v;
 178 }
 179 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 180 {
 181         *(volatile unsigned long __force *)addr = v;
 182 }
 183
 184
 185 /*
 186  *
 187  * PCI PIO and MMIO accessors.
 188  *
 189  */
 190
 191 #include <asm/eeh.h>
 192
 193 /* Shortcut to the MMIO argument pointer */
 194 #define PCI_IO_ADDR     volatile void __iomem *
 195
 196 /* Indirect IO address tokens:
 197  *
 198  * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
 199  * on all IOs.
 200  *
 201  * To help platforms who may need to differenciate MMIO addresses in
 202  * their hooks, a bitfield is reserved for use by the platform near the
 203  * top of MMIO addresses (not PIO, those have to cope the hard way).
 204  *
 205  * This bit field is 12 bits and is at the top of the IO virtual
 206  * addresses PCI_IO_INDIRECT_TOKEN_MASK.
 207  *
 208  * The kernel virtual space is thus:
 209  *
 210  *  0xD000000000000000          : vmalloc
 211  *  0xD000080000000000          : PCI PHB IO space
 212  *  0xD000080080000000          : ioremap
 213  *  0xD0000fffffffffff          : end of ioremap region
 214  *
 215  * Since the top 4 bits are reserved as the region ID, we use thus
 216  * the next 12 bits and keep 4 bits available for the future if the
 217  * virtual address space is ever to be extended.
 218  *
 219  * The direct IO mapping operations will then mask off those bits
 220  * before doing the actual access, though that only happen when
 221  * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
 222  * mechanism
 223  */
 224
 225 #ifdef CONFIG_PPC_INDIRECT_IO
 226 #define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
 227 #define PCI_IO_IND_TOKEN_SHIFT  48
 228 #define PCI_FIX_ADDR(addr)                                              \
 229         ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
 230 #define PCI_GET_ADDR_TOKEN(addr)                                        \
 231         (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
 232                 PCI_IO_IND_TOKEN_SHIFT)
 233 #define PCI_SET_ADDR_TOKEN(addr, token)                                 \
 234 do {                                                                    \
 235         unsigned long __a = (unsigned long)(addr);                      \
 236         __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
 237         __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
 238         (addr) = (void __iomem *)__a;                                   \
 239 } while(0)
 240 #else
 241 #define PCI_FIX_ADDR(addr) (addr)
 242 #endif
 243
 244 /* The "__do_*" operations below provide the actual "base" implementation
 245  * for each of the defined acccessor. Some of them use the out_* functions
 246  * directly, some of them still use EEH, though we might change that in the
 247  * future. Those macros below provide the necessary argument swapping and
 248  * handling of the IO base for PIO.
 249  *
 250  * They are themselves used by the macros that define the actual accessors
 251  * and can be used by the hooks if any.
 252  *
 253  * Note that PIO operations are always defined in terms of their corresonding
 254  * MMIO operations. That allows platforms like iSeries who want to modify the
 255  * behaviour of both to only hook on the MMIO version and get both. It's also
 256  * possible to hook directly at the toplevel PIO operation if they have to
 257  * be handled differently
 258  */
 259 #define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
 260 #define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
 261 #define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
 262 #define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
 263 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
 264 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
 265 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
 266 #define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
 267 #define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
 268 #define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
 269 #define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
 270 #define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
 271 #define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
 272 #define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
 273
 274 #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)pci_io_base+port);
 275 #define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)pci_io_base+port);
 276 #define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)pci_io_base+port);
 277 #define __do_inb(port)          readb((PCI_IO_ADDR)pci_io_base + port);
 278 #define __do_inw(port)          readw((PCI_IO_ADDR)pci_io_base + port);
 279 #define __do_inl(port)          readl((PCI_IO_ADDR)pci_io_base + port);
 280
 281 #define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
 282 #define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
 283 #define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
 284 #define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
 285 #define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
 286 #define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
 287
 288 #define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)pci_io_base+(p), (b), (n))
 289 #define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)pci_io_base+(p), (b), (n))
 290 #define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)pci_io_base+(p), (b), (n))
 291 #define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)pci_io_base+(p),(b),(n))
 292 #define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)pci_io_base+(p),(b),(n))
 293 #define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)pci_io_base+(p),(b),(n))
 294
 295 #define __do_memset_io(addr, c, n)      eeh_memset_io(PCI_FIX_ADDR(addr), c, n)
 296 #define __do_memcpy_fromio(dst, src, n) eeh_memcpy_fromio(dst, \
 297                                                 PCI_FIX_ADDR(src), n)
 298 #define __do_memcpy_toio(dst, src, n)   eeh_memcpy_toio(PCI_FIX_ADDR(dst), \
 299                                                 src, n)
 300
 301 #ifdef CONFIG_PPC_INDIRECT_IO
 302 #define DEF_PCI_HOOK(x)         x
 303 #else
 304 #define DEF_PCI_HOOK(x)         NULL
 305 #endif
 306
 307 /* Structure containing all the hooks */
 308 extern struct ppc_pci_io {
 309
 310 #define DEF_PCI_AC_RET(name, ret, at, al)       ret (*name) at;
 311 #define DEF_PCI_AC_NORET(name, at, al)          void (*name) at;
 312
 313 #include <asm/io-defs.h>
 314
 315 #undef DEF_PCI_AC_RET
 316 #undef DEF_PCI_AC_NORET
 317
 318 } ppc_pci_io;
 319
 320 /* The inline wrappers */
 321 #define DEF_PCI_AC_RET(name, ret, at, al)                       \
 322 static inline ret name at                                       \
 323 {                                                               \
 324         if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
 325                 return ppc_pci_io.name al;                      \
 326         return __do_##name al;                                  \
 327 }
 328
 329 #define DEF_PCI_AC_NORET(name, at, al)                          \
 330 static inline void name at                                      \
 331 {                                                               \
 332         if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
 333                 ppc_pci_io.name al;                             \
 334         else                                                    \
 335                 __do_##name al;                                 \
 336 }
 337
 338 #include <asm/io-defs.h>
 339
 340 #undef DEF_PCI_AC_RET
 341 #undef DEF_PCI_AC_NORET
 342
 343 /* Some drivers check for the presence of readq & writeq with
 344  * a #ifdef, so we make them happy here.
 345  */
 346 #define readq   readq
 347 #define writeq  writeq
 348
 349 /* Nothing to do for cache stuff x*/
 350
 351 #define dma_cache_inv(_start,_size)             do { } while (0)
 352 #define dma_cache_wback(_start,_size)           do { } while (0)
 353 #define dma_cache_wback_inv(_start,_size)       do { } while (0)
 354
 355
 356 /*
 357  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 358  * access
 359  */
 360 #define xlate_dev_mem_ptr(p)    __va(p)
 361
 362 /*
 363  * Convert a virtual cached pointer to an uncached pointer
 364  */
 365 #define xlate_dev_kmem_ptr(p)   p
 366
 367 /*
 368  * We don't do relaxed operations yet, at least not with this semantic
 369  */
 370 #define readb_relaxed(addr) readb(addr)
 371 #define readw_relaxed(addr) readw(addr)
 372 #define readl_relaxed(addr) readl(addr)
 373 #define readq_relaxed(addr) readq(addr)
 374
 375 /*
 376  * Enforce synchronisation of stores vs. spin_unlock
 377  * (this does it explicitely, though our implementation of spin_unlock
 378  * does it implicitely too)
 379  */
 380 static inline void mmiowb(void)
 381 {
 382         unsigned long tmp;
 383
 384         __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
 385         : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
 386         : "memory");
 387 }
 388
 389 static inline void iosync(void)
 390 {
 391         __asm__ __volatile__ ("sync" : : : "memory");
 392 }
 393
 394 /* Enforce in-order execution of data I/O.
 395  * No distinction between read/write on PPC; use eieio for all three.
 396  * Those are fairly week though. They don't provide a barrier between
 397  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
 398  * they only provide barriers between 2 __raw MMIO operations and
 399  * possibly break write combining.
 400  */
 401 #define iobarrier_rw() eieio()
 402 #define iobarrier_r()  eieio()
 403 #define iobarrier_w()  eieio()
 404
 405
 406 /*
 407  * output pause versions need a delay at least for the
 408  * w83c105 ide controller in a p610.
 409  */
 410 #define inb_p(port)             inb(port)
 411 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
 412 #define inw_p(port)             inw(port)
 413 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
 414 #define inl_p(port)             inl(port)
 415 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
 416
 417
 418 #define IO_SPACE_LIMIT ~(0UL)
 419
 420
 421 /**
 422  * ioremap     -   map bus memory into CPU space
 423  * @address:   bus address of the memory
 424  * @size:      size of the resource to map
 425  *
 426  * ioremap performs a platform specific sequence of operations to
 427  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 428  * writew/writel functions and the other mmio helpers. The returned
 429  * address is not guaranteed to be usable directly as a virtual
 430  * address.
 431  *
 432  * We provide a few variations of it:
 433  *
 434  * * ioremap is the standard one and provides non-cacheable guarded mappings
 435  *   and can be hooked by the platform via ppc_md
 436  *
 437  * * ioremap_flags allows to specify the page flags as an argument and can
 438  *   also be hooked by the platform via ppc_md
 439  *
 440  * * ioremap_nocache is identical to ioremap
 441  *
 442  * * iounmap undoes such a mapping and can be hooked
 443  *
 444  * * __ioremap_explicit (and the pending __iounmap_explicit) are low level
 445  *   functions to create hand-made mappings for use only by the PCI code
 446  *   and cannot currently be hooked.
 447  *
 448  * * __ioremap is the low level implementation used by ioremap and
 449  *   ioremap_flags and cannot be hooked (but can be used by a hook on one
 450  *   of the previous ones)
 451  *
 452  * * __iounmap, is the low level implementation used by iounmap and cannot
 453  *   be hooked (but can be used by a hook on iounmap)
 454  *
 455  */
 456 extern void __iomem *ioremap(unsigned long address, unsigned long size);
 457 extern void __iomem *ioremap_flags(unsigned long address, unsigned long size,
 458                                    unsigned long flags);
 459 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 460 extern void iounmap(void __iomem *addr);
 461
 462 extern void __iomem *__ioremap(unsigned long address, unsigned long size,
 463                                unsigned long flags);
 464 extern void __iounmap(void __iomem *addr);
 465
 466 extern int __ioremap_explicit(unsigned long p_addr, unsigned long v_addr,
 467                               unsigned long size, unsigned long flags);
 468 extern int __iounmap_explicit(void __iomem *start, unsigned long size);
 469
 470 extern void __iomem * reserve_phb_iospace(unsigned long size);
 471
 472
 473 /*
 474  * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
 475  * which needs some additional definitions here. They basically allow PIO
 476  * space overall to be 1GB. This will work as long as we never try to use
 477  * iomap to map MMIO below 1GB which should be fine on ppc64
 478  */
 479 #define HAVE_ARCH_PIO_SIZE              1
 480 #define PIO_OFFSET                      0x00000000UL
 481 #define PIO_MASK                        0x3fffffffUL
 482 #define PIO_RESERVED                    0x40000000UL
 483
 484 #define mmio_read16be(addr)             readw_be(addr)
 485 #define mmio_read32be(addr)             readl_be(addr)
 486 #define mmio_write16be(val, addr)       writew_be(val, addr)
 487 #define mmio_write32be(val, addr)       writel_be(val, addr)
 488 #define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
 489 #define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
 490 #define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
 491 #define mmio_outsb(addr, src, count)    writesb(addr, src, count)
 492 #define mmio_outsw(addr, src, count)    writesw(addr, src, count)
 493 #define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 494
 495 /**
 496  *      virt_to_phys    -       map virtual addresses to physical
 497  *      @address: address to remap
 498  *
 499  *      The returned physical address is the physical (CPU) mapping for
 500  *      the memory address given. It is only valid to use this function on
 501  *      addresses directly mapped or allocated via kmalloc.
 502  *
 503  *      This function does not give bus mappings for DMA transfers. In
 504  *      almost all conceivable cases a device driver should not be using
 505  *      this function
 506  */
 507 static inline unsigned long virt_to_phys(volatile void * address)
 508 {
 509         return __pa((unsigned long)address);
 510 }
 511
 512 /**
 513  *      phys_to_virt    -       map physical address to virtual
 514  *      @address: address to remap
 515  *
 516  *      The returned virtual address is a current CPU mapping for
 517  *      the memory address given. It is only valid to use this function on
 518  *      addresses that have a kernel mapping
 519  *
 520  *      This function does not handle bus mappings for DMA transfers. In
 521  *      almost all conceivable cases a device driver should not be using
 522  *      this function
 523  */
 524 static inline void * phys_to_virt(unsigned long address)
 525 {
 526         return (void *)__va(address);
 527 }
 528
 529 /*
 530  * Change "struct page" to physical address.
 531  */
 532 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 533
 534 /* We do NOT want virtual merging, it would put too much pressure on
 535  * our iommu allocator. Instead, we want drivers to be smart enough
 536  * to coalesce sglists that happen to have been mapped in a contiguous
 537  * way by the iommu
 538  */
 539 #define BIO_VMERGE_BOUNDARY     0
 540
 541 #endif /* __KERNEL__ */
 542
 543 #endif /* CONFIG_PPC64 */
 544 #endif /* _ASM_POWERPC_IO_H */