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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - include/asm-powerpc/system.h
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
4 #ifndef _ASM_POWERPC_SYSTEM_H
5 #define _ASM_POWERPC_SYSTEM_H
7 #include <linux/kernel.h>
9 #include <asm/hw_irq.h>
13 * The sync instruction guarantees that all memory accesses initiated
14 * by this processor have been performed (with respect to all other
15 * mechanisms that access memory). The eieio instruction is a barrier
16 * providing an ordering (separately) for (a) cacheable stores and (b)
17 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 * mb() prevents loads and stores being reordered across this point.
20 * rmb() prevents loads being reordered across this point.
21 * wmb() prevents stores being reordered across this point.
22 * read_barrier_depends() prevents data-dependent loads being reordered
23 * across this point (nop on PPC).
25 * We have to use the sync instructions for mb(), since lwsync doesn't
26 * order loads with respect to previous stores. Lwsync is fine for
27 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
30 * For wmb(), we use sync since wmb is used in drivers to order
31 * stores to system memory with respect to writes to the device.
32 * However, smp_wmb() can be a lighter-weight eieio barrier on
33 * SMP since it is only used to order updates to system memory.
35 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
36 #define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
37 #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
38 #define read_barrier_depends() do { } while(0)
40 #define set_mb(var, value) do { var = value; mb(); } while (0)
43 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
46 #define smp_rmb() rmb()
47 #define smp_wmb() eieio()
48 #define smp_read_barrier_depends() read_barrier_depends()
50 #define smp_mb() barrier()
51 #define smp_rmb() barrier()
52 #define smp_wmb() barrier()
53 #define smp_read_barrier_depends() do { } while(0)
54 #endif /* CONFIG_SMP */
57 * This is a barrier which prevents following instructions from being
58 * started until the value of the argument x is known. For example, if
59 * x is a variable loaded from memory, this prevents following
60 * instructions from being executed until the load has been performed.
62 #define data_barrier(x) \
63 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
68 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
70 extern int (*__debugger
)(struct pt_regs
*regs
);
71 extern int (*__debugger_ipi
)(struct pt_regs
*regs
);
72 extern int (*__debugger_bpt
)(struct pt_regs
*regs
);
73 extern int (*__debugger_sstep
)(struct pt_regs
*regs
);
74 extern int (*__debugger_iabr_match
)(struct pt_regs
*regs
);
75 extern int (*__debugger_dabr_match
)(struct pt_regs
*regs
);
76 extern int (*__debugger_fault_handler
)(struct pt_regs
*regs
);
78 #define DEBUGGER_BOILERPLATE(__NAME) \
79 static inline int __NAME(struct pt_regs *regs) \
81 if (unlikely(__ ## __NAME)) \
82 return __ ## __NAME(regs); \
86 DEBUGGER_BOILERPLATE(debugger
)
87 DEBUGGER_BOILERPLATE(debugger_ipi
)
88 DEBUGGER_BOILERPLATE(debugger_bpt
)
89 DEBUGGER_BOILERPLATE(debugger_sstep
)
90 DEBUGGER_BOILERPLATE(debugger_iabr_match
)
91 DEBUGGER_BOILERPLATE(debugger_dabr_match
)
92 DEBUGGER_BOILERPLATE(debugger_fault_handler
)
95 static inline int debugger(struct pt_regs
*regs
) { return 0; }
96 static inline int debugger_ipi(struct pt_regs
*regs
) { return 0; }
97 static inline int debugger_bpt(struct pt_regs
*regs
) { return 0; }
98 static inline int debugger_sstep(struct pt_regs
*regs
) { return 0; }
99 static inline int debugger_iabr_match(struct pt_regs
*regs
) { return 0; }
100 static inline int debugger_dabr_match(struct pt_regs
*regs
) { return 0; }
101 static inline int debugger_fault_handler(struct pt_regs
*regs
) { return 0; }
104 extern int set_dabr(unsigned long dabr
);
105 extern void print_backtrace(unsigned long *);
106 extern void show_regs(struct pt_regs
* regs
);
107 extern void flush_instruction_cache(void);
108 extern void hard_reset_now(void);
109 extern void poweroff_now(void);
112 extern long _get_L2CR(void);
113 extern long _get_L3CR(void);
114 extern void _set_L2CR(unsigned long);
115 extern void _set_L3CR(unsigned long);
117 #define _get_L2CR() 0L
118 #define _get_L3CR() 0L
119 #define _set_L2CR(val) do { } while(0)
120 #define _set_L3CR(val) do { } while(0)
123 extern void via_cuda_init(void);
124 extern void read_rtc_time(void);
125 extern void pmac_find_display(void);
126 extern void giveup_fpu(struct task_struct
*);
127 extern void disable_kernel_fp(void);
128 extern void enable_kernel_fp(void);
129 extern void flush_fp_to_thread(struct task_struct
*);
130 extern void enable_kernel_altivec(void);
131 extern void giveup_altivec(struct task_struct
*);
132 extern void load_up_altivec(struct task_struct
*);
133 extern int emulate_altivec(struct pt_regs
*);
134 extern void enable_kernel_spe(void);
135 extern void giveup_spe(struct task_struct
*);
136 extern void load_up_spe(struct task_struct
*);
137 extern int fix_alignment(struct pt_regs
*);
138 extern void cvt_fd(float *from
, double *to
, struct thread_struct
*thread
);
139 extern void cvt_df(double *from
, float *to
, struct thread_struct
*thread
);
142 extern void discard_lazy_cpu_state(void);
144 static inline void discard_lazy_cpu_state(void)
149 #ifdef CONFIG_ALTIVEC
150 extern void flush_altivec_to_thread(struct task_struct
*);
152 static inline void flush_altivec_to_thread(struct task_struct
*t
)
158 extern void flush_spe_to_thread(struct task_struct
*);
160 static inline void flush_spe_to_thread(struct task_struct
*t
)
165 extern int call_rtas(const char *, int, int, unsigned long *, ...);
166 extern void cacheable_memzero(void *p
, unsigned int nb
);
167 extern void *cacheable_memcpy(void *, const void *, unsigned int);
168 extern int do_page_fault(struct pt_regs
*, unsigned long, unsigned long);
169 extern void bad_page_fault(struct pt_regs
*, unsigned long, int);
170 extern int die(const char *, struct pt_regs
*, long);
171 extern void _exception(int, struct pt_regs
*, int, unsigned long);
172 extern void _nmask_and_or_msr(unsigned long nmask
, unsigned long or_val
);
174 #ifdef CONFIG_BOOKE_WDT
175 extern u32 booke_wdt_enabled
;
176 extern u32 booke_wdt_period
;
177 #endif /* CONFIG_BOOKE_WDT */
180 extern void note_scsi_host(struct device_node
*, void *);
182 extern struct task_struct
*__switch_to(struct task_struct
*,
183 struct task_struct
*);
184 #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
186 struct thread_struct
;
187 extern struct task_struct
*_switch(struct thread_struct
*prev
,
188 struct thread_struct
*next
);
190 extern unsigned int rtas_data
;
191 extern int mem_init_done
; /* set on boot once kmalloc can be called */
192 extern unsigned long memory_limit
;
193 extern unsigned long klimit
;
195 extern void *alloc_maybe_bootmem(size_t size
, gfp_t mask
);
196 extern void *zalloc_maybe_bootmem(size_t size
, gfp_t mask
);
198 extern int powersave_nap
; /* set if nap mode can be used in idle loop */
203 * Changes the memory location '*ptr' to be val and returns
204 * the previous value stored there.
206 static __inline__
unsigned long
207 __xchg_u32(volatile void *p
, unsigned long val
)
211 __asm__
__volatile__(
213 "1: lwarx %0,0,%2 \n"
218 : "=&r" (prev
), "+m" (*(volatile unsigned int *)p
)
228 * Changes the memory location '*ptr' to be val and returns
229 * the previous value stored there.
231 static __inline__
unsigned long
232 __xchg_u32_local(volatile void *p
, unsigned long val
)
236 __asm__
__volatile__(
237 "1: lwarx %0,0,%2 \n"
241 : "=&r" (prev
), "+m" (*(volatile unsigned int *)p
)
249 static __inline__
unsigned long
250 __xchg_u64(volatile void *p
, unsigned long val
)
254 __asm__
__volatile__(
256 "1: ldarx %0,0,%2 \n"
261 : "=&r" (prev
), "+m" (*(volatile unsigned long *)p
)
268 static __inline__
unsigned long
269 __xchg_u64_local(volatile void *p
, unsigned long val
)
273 __asm__
__volatile__(
274 "1: ldarx %0,0,%2 \n"
278 : "=&r" (prev
), "+m" (*(volatile unsigned long *)p
)
287 * This function doesn't exist, so you'll get a linker error
288 * if something tries to do an invalid xchg().
290 extern void __xchg_called_with_bad_pointer(void);
292 static __inline__
unsigned long
293 __xchg(volatile void *ptr
, unsigned long x
, unsigned int size
)
297 return __xchg_u32(ptr
, x
);
300 return __xchg_u64(ptr
, x
);
303 __xchg_called_with_bad_pointer();
307 static __inline__
unsigned long
308 __xchg_local(volatile void *ptr
, unsigned long x
, unsigned int size
)
312 return __xchg_u32_local(ptr
, x
);
315 return __xchg_u64_local(ptr
, x
);
318 __xchg_called_with_bad_pointer();
321 #define xchg(ptr,x) \
323 __typeof__(*(ptr)) _x_ = (x); \
324 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
327 #define xchg_local(ptr,x) \
329 __typeof__(*(ptr)) _x_ = (x); \
330 (__typeof__(*(ptr))) __xchg_local((ptr), \
331 (unsigned long)_x_, sizeof(*(ptr))); \
335 * Compare and exchange - if *p == old, set it to new,
336 * and return the old value of *p.
338 #define __HAVE_ARCH_CMPXCHG 1
340 static __inline__
unsigned long
341 __cmpxchg_u32(volatile unsigned int *p
, unsigned long old
, unsigned long new)
345 __asm__
__volatile__ (
347 "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
356 : "=&r" (prev
), "+m" (*p
)
357 : "r" (p
), "r" (old
), "r" (new)
363 static __inline__
unsigned long
364 __cmpxchg_u32_local(volatile unsigned int *p
, unsigned long old
,
369 __asm__
__volatile__ (
370 "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
378 : "=&r" (prev
), "+m" (*p
)
379 : "r" (p
), "r" (old
), "r" (new)
386 static __inline__
unsigned long
387 __cmpxchg_u64(volatile unsigned long *p
, unsigned long old
, unsigned long new)
391 __asm__
__volatile__ (
393 "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
401 : "=&r" (prev
), "+m" (*p
)
402 : "r" (p
), "r" (old
), "r" (new)
408 static __inline__
unsigned long
409 __cmpxchg_u64_local(volatile unsigned long *p
, unsigned long old
,
414 __asm__
__volatile__ (
415 "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
422 : "=&r" (prev
), "+m" (*p
)
423 : "r" (p
), "r" (old
), "r" (new)
430 /* This function doesn't exist, so you'll get a linker error
431 if something tries to do an invalid cmpxchg(). */
432 extern void __cmpxchg_called_with_bad_pointer(void);
434 static __inline__
unsigned long
435 __cmpxchg(volatile void *ptr
, unsigned long old
, unsigned long new,
440 return __cmpxchg_u32(ptr
, old
, new);
443 return __cmpxchg_u64(ptr
, old
, new);
446 __cmpxchg_called_with_bad_pointer();
450 static __inline__
unsigned long
451 __cmpxchg_local(volatile void *ptr
, unsigned long old
, unsigned long new,
456 return __cmpxchg_u32_local(ptr
, old
, new);
459 return __cmpxchg_u64_local(ptr
, old
, new);
462 __cmpxchg_called_with_bad_pointer();
466 #define cmpxchg(ptr, o, n) \
468 __typeof__(*(ptr)) _o_ = (o); \
469 __typeof__(*(ptr)) _n_ = (n); \
470 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
471 (unsigned long)_n_, sizeof(*(ptr))); \
475 #define cmpxchg_local(ptr, o, n) \
477 __typeof__(*(ptr)) _o_ = (o); \
478 __typeof__(*(ptr)) _n_ = (n); \
479 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
480 (unsigned long)_n_, sizeof(*(ptr))); \
485 * We handle most unaligned accesses in hardware. On the other hand
486 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
487 * powers of 2 writes until it reaches sufficient alignment).
489 * Based on this we disable the IP header alignment in network drivers.
490 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
491 * cacheline alignment of buffers.
493 #define NET_IP_ALIGN 0
494 #define NET_SKB_PAD L1_CACHE_BYTES
496 #define cmpxchg64(ptr, o, n) \
498 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
499 cmpxchg((ptr), (o), (n)); \
501 #define cmpxchg64_local(ptr, o, n) \
503 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
504 cmpxchg_local((ptr), (o), (n)); \
507 #include <asm-generic/cmpxchg-local.h>
508 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
511 #define arch_align_stack(x) (x)
513 /* Used in very early kernel initialization. */
514 extern unsigned long reloc_offset(void);
515 extern unsigned long add_reloc_offset(unsigned long);
516 extern void reloc_got2(unsigned long);
518 #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
520 static inline void create_instruction(unsigned long addr
, unsigned int instr
)
523 p
= (unsigned int *)addr
;
525 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p
));
528 /* Flags for create_branch:
529 * "b" == create_branch(addr, target, 0);
530 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
531 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
532 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
534 #define BRANCH_SET_LINK 0x1
535 #define BRANCH_ABSOLUTE 0x2
537 static inline void create_branch(unsigned long addr
,
538 unsigned long target
, int flags
)
540 unsigned int instruction
;
542 if (! (flags
& BRANCH_ABSOLUTE
))
543 target
= target
- addr
;
545 /* Mask out the flags and target, so they don't step on each other. */
546 instruction
= 0x48000000 | (flags
& 0x3) | (target
& 0x03FFFFFC);
548 create_instruction(addr
, instruction
);
551 static inline void create_function_call(unsigned long addr
, void * func
)
553 unsigned long func_addr
;
557 * On PPC64 the function pointer actually points to the function's
558 * descriptor. The first entry in the descriptor is the address
559 * of the function text.
561 func_addr
= *(unsigned long *)func
;
563 func_addr
= (unsigned long)func
;
565 create_branch(addr
, func_addr
, BRANCH_SET_LINK
);
568 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
569 extern void account_system_vtime(struct task_struct
*);
572 extern struct dentry
*powerpc_debugfs_root
;
574 #endif /* __KERNEL__ */
575 #endif /* _ASM_POWERPC_SYSTEM_H */