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1 #ifndef __ASM_SH64_CACHE_H
2 #define __ASM_SH64_CACHE_H
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * include/asm-sh64/cache.h
11 * Copyright (C) 2000, 2001 Paolo Alberelli
12 * Copyright (C) 2003, 2004 Paul Mundt
15 #include <asm/cacheflush.h>
17 #define L1_CACHE_SHIFT 5
18 /* bytes per L1 cache line */
19 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
20 #define L1_CACHE_ALIGN_MASK (~(L1_CACHE_BYTES - 1))
21 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES - 1)) & L1_CACHE_ALIGN_MASK)
22 #define L1_CACHE_SIZE_BYTES (L1_CACHE_BYTES << 10)
23 /* Largest L1 which this arch supports */
24 #define L1_CACHE_SHIFT_MAX 5
27 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
29 #define __cacheline_aligned \
30 __attribute__((__aligned__(L1_CACHE_BYTES), \
31 __section__(".data.cacheline_aligned")))
37 #define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */
38 #define ICCR_REG0 0 /* Register 0 offset */
39 #define ICCR_REG1 1 /* Register 1 offset */
40 #define ICCR0 ICCR_BASE+ICCR_REG0
41 #define ICCR1 ICCR_BASE+ICCR_REG1
43 #define ICCR0_OFF 0x0 /* Set ICACHE off */
44 #define ICCR0_ON 0x1 /* Set ICACHE on */
45 #define ICCR0_ICI 0x2 /* Invalidate all in IC */
47 #define ICCR1_NOLOCK 0x0 /* Set No Locking */
49 #define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */
50 #define OCCR_REG0 0 /* Register 0 offset */
51 #define OCCR_REG1 1 /* Register 1 offset */
52 #define OCCR0 OCCR_BASE+OCCR_REG0
53 #define OCCR1 OCCR_BASE+OCCR_REG1
55 #define OCCR0_OFF 0x0 /* Set OCACHE off */
56 #define OCCR0_ON 0x1 /* Set OCACHE on */
57 #define OCCR0_OCI 0x2 /* Invalidate all in OC */
58 #define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
59 #define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
61 #define OCCR1_NOLOCK 0x0 /* Set No Locking */
66 * A bit of description here, for neff=32.
68 * |<--- tag (19 bits) --->|
69 * +-----------------------------+-----------------+------+----------+------+
70 * | | | ways |set index |offset|
71 * +-----------------------------+-----------------+------+----------+------+
72 * ^ 2 bits 8 bits 5 bits
75 * Cacheline size is based on offset: 5 bits = 32 bytes per line
76 * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
77 * have a broader space for registers. These are outlined by
78 * CACHE_?C_*_STEP below.
82 /* Valid and Dirty bits */
83 #define SH_CACHE_VALID (1LL<<0)
84 #define SH_CACHE_UPDATED (1LL<<57)
87 #define SH_CACHE_MODE_WT (1LL<<0)
88 #define SH_CACHE_MODE_WB (1LL<<1)
93 * Cache information structure.
95 * Defined for both I and D cache, per-processor.
102 unsigned int way_shift
;
103 unsigned int entry_shift
;
104 unsigned int set_shift
;
105 unsigned int way_step_shift
;
106 unsigned int asid_shift
;
108 unsigned int way_ofs
;
110 unsigned int asid_mask
;
111 unsigned int idx_mask
;
112 unsigned int epn_mask
;
117 #endif /* __ASSEMBLY__ */
119 /* Instruction cache */
120 #define CACHE_IC_ADDRESS_ARRAY 0x01000000
123 #define CACHE_OC_ADDRESS_ARRAY 0x01800000
125 /* These declarations relate to cache 'synonyms' in the operand cache. A
126 'synonym' occurs where effective address bits overlap between those used for
127 indexing the cache sets and those passed to the MMU for translation. In the
128 case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
130 #define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
131 #define CACHE_OC_SYN_SHIFT 12
132 /* Mask to select synonym bit(s) */
133 #define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
137 * Instruction cache can't be invalidated based on physical addresses.
138 * No Instruction Cache defines required, then.
141 #endif /* __ASM_SH64_CACHE_H */