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1 #ifndef __ASM_SH64_IRQ_H
2 #define __ASM_SH64_IRQ_H
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * include/asm-sh64/irq.h
11 * Copyright (C) 2000, 2001 Paolo Alberelli
15 #include <linux/config.h>
18 * Encoded IRQs are not considered worth to be supported.
19 * Main reason is that there's no per-encoded-interrupt
20 * enable/disable mechanism (as there was in SH3/4).
21 * An all enabled/all disabled is worth only if there's
22 * a cascaded IC to disable/enable/ack on. Until such
23 * IC is available there's no such support.
25 * Presumably Encoded IRQs may use extra IRQs beyond 64,
26 * below. Some logic must be added to cope with IRQ_IRL?
27 * in an exclusive way.
29 * Priorities are set at Platform level, when IRQ_IRL0-3
30 * are set to 0 Encoding is allowed. Otherwise it's not
34 /* Independent IRQs */
74 #define NR_INTC_IRQS 64
76 #ifdef CONFIG_SH_CAYMAN
77 #define NR_EXT_IRQS 32
78 #define START_EXT_IRQS 64
80 /* PCI bus 2 uses encoded external interrupts on the Cayman board */
81 #define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0)
82 #define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1)
83 #define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2)
84 #define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3)
86 #define I8042_KBD_IRQ (START_EXT_IRQS + 2)
87 #define I8042_AUX_IRQ (START_EXT_IRQS + 6)
89 #define IRQ_CFCARD (START_EXT_IRQS + 7)
90 #define IRQ_PCMCIA (0)
96 #define NR_IRQS (NR_INTC_IRQS+NR_EXT_IRQS)
99 /* Default IRQs, fixed */
100 #define TIMER_IRQ IRQ_TUNI0
101 #define RTC_IRQ IRQ_CUI
103 /* Default Priorities, Platform may choose differently */
104 #define NO_PRIORITY 0 /* Disabled */
105 #define TIMER_PRIORITY 2
106 #define RTC_PRIORITY TIMER_PRIORITY
107 #define SCIF_PRIORITY 3
108 #define INTD_PRIORITY 3
109 #define IRL3_PRIORITY 4
110 #define INTC_PRIORITY 6
111 #define IRL2_PRIORITY 7
112 #define INTB_PRIORITY 9
113 #define IRL1_PRIORITY 10
114 #define INTA_PRIORITY 12
115 #define IRL0_PRIORITY 13
116 #define TOP_PRIORITY 15
118 extern void disable_irq(unsigned int);
119 extern void disable_irq_nosync(unsigned int);
120 extern void enable_irq(unsigned int);
122 extern int intc_evt_to_irq
[(0xE20/0x20)+1];
123 int intc_irq_describe(char* p
, int irq
);
125 #define irq_canonicalize(irq) (irq)
127 #ifdef CONFIG_SH_CAYMAN
128 int cayman_irq_demux(int evt
);
129 int cayman_irq_describe(char* p
, int irq
);
130 #define irq_demux(x) cayman_irq_demux(x)
131 #define irq_describe(p, x) cayman_irq_describe(p, x)
133 #define irq_demux(x) (intc_evt_to_irq[x])
134 #define irq_describe(p, x) intc_irq_describe(p, x)
138 * Function for "on chip support modules".
142 * SH-5 supports Priority based interrupts only.
143 * Interrupt priorities are defined at platform level.
145 #define set_ipr_data(a, b, c, d)
146 #define make_ipr_irq(a)
147 #define make_imask_irq(a)
149 #endif /* __ASM_SH64_IRQ_H */