include/asm-sparc64/mmu_context.h

   1 /* $Id: mmu_context.h,v 1.54 2002/02/09 19:49:31 davem Exp $ */
   2 #ifndef __SPARC64_MMU_CONTEXT_H
   3 #define __SPARC64_MMU_CONTEXT_H
   4
   5 /* Derived heavily from Linus's Alpha/AXP ASN code... */
   6
   7 #ifndef __ASSEMBLY__
   8
   9 #include <linux/spinlock.h>
  10 #include <asm/system.h>
  11 #include <asm/spitfire.h>
  12
  13 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  14 {
  15 }
  16
  17 extern spinlock_t ctx_alloc_lock;
  18 extern unsigned long tlb_context_cache;
  19 extern unsigned long mmu_context_bmap[];
  20
  21 extern void get_new_mmu_context(struct mm_struct *mm);
  22 #ifdef CONFIG_SMP
  23 extern void smp_new_mmu_context_version(void);
  24 #else
  25 #define smp_new_mmu_context_version() do { } while (0)
  26 #endif
  27
  28 extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
  29 extern void destroy_context(struct mm_struct *mm);
  30
  31 extern void __tsb_context_switch(unsigned long pgd_pa,
  32                                  unsigned long tsb_reg,
  33                                  unsigned long tsb_vaddr,
  34                                  unsigned long tsb_pte,
  35                                  unsigned long tsb_descr_pa);
  36
  37 static inline void tsb_context_switch(struct mm_struct *mm)
  38 {
  39         __tsb_context_switch(__pa(mm->pgd), mm->context.tsb_reg_val,
  40                              mm->context.tsb_map_vaddr,
  41                              mm->context.tsb_map_pte,
  42                              __pa(&mm->context.tsb_descr));
  43 }
  44
  45 extern void tsb_grow(struct mm_struct *mm, unsigned long mm_rss, gfp_t gfp_flags);
  46 #ifdef CONFIG_SMP
  47 extern void smp_tsb_sync(struct mm_struct *mm);
  48 #else
  49 #define smp_tsb_sync(__mm) do { } while (0)
  50 #endif
  51
  52 /* Set MMU context in the actual hardware. */
  53 #define load_secondary_context(__mm) \
  54         __asm__ __volatile__( \
  55         "\n661: stxa            %0, [%1] %2\n" \
  56         "       .section        .sun4v_1insn_patch, \"ax\"\n" \
  57         "       .word           661b\n" \
  58         "       stxa            %0, [%1] %3\n" \
  59         "       .previous\n" \
  60         "       flush           %%g6\n" \
  61         : /* No outputs */ \
  62         : "r" (CTX_HWBITS((__mm)->context)), \
  63           "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
  64
  65 extern void __flush_tlb_mm(unsigned long, unsigned long);
  66
  67 /* Switch the current MM context.  Interrupts are disabled.  */
  68 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
  69 {
  70         unsigned long ctx_valid;
  71         int cpu;
  72
  73         spin_lock(&mm->context.lock);
  74         ctx_valid = CTX_VALID(mm->context);
  75         if (!ctx_valid)
  76                 get_new_mmu_context(mm);
  77         spin_unlock(&mm->context.lock);
  78
  79         if (!ctx_valid || (old_mm != mm)) {
  80                 load_secondary_context(mm);
  81                 tsb_context_switch(mm);
  82         }
  83
  84         /* Even if (mm == old_mm) we _must_ check
  85          * the cpu_vm_mask.  If we do not we could
  86          * corrupt the TLB state because of how
  87          * smp_flush_tlb_{page,range,mm} on sparc64
  88          * and lazy tlb switches work. -DaveM
  89          */
  90         cpu = smp_processor_id();
  91         if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
  92                 cpu_set(cpu, mm->cpu_vm_mask);
  93                 __flush_tlb_mm(CTX_HWBITS(mm->context),
  94                                SECONDARY_CONTEXT);
  95         }
  96 }
  97
  98 #define deactivate_mm(tsk,mm)   do { } while (0)
  99
 100 /* Activate a new MM instance for the current task. */
 101 static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
 102 {
 103         unsigned long flags;
 104         int cpu;
 105
 106         spin_lock_irqsave(&mm->context.lock, flags);
 107         if (!CTX_VALID(mm->context))
 108                 get_new_mmu_context(mm);
 109         cpu = smp_processor_id();
 110         if (!cpu_isset(cpu, mm->cpu_vm_mask))
 111                 cpu_set(cpu, mm->cpu_vm_mask);
 112         spin_unlock_irqrestore(&mm->context.lock, flags);
 113
 114         load_secondary_context(mm);
 115         __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
 116         tsb_context_switch(mm);
 117 }
 118
 119 #endif /* !(__ASSEMBLY__) */
 120
 121 #endif /* !(__SPARC64_MMU_CONTEXT_H) */