include/asm-sparc64/mmu_context.h

   1 /* $Id: mmu_context.h,v 1.54 2002/02/09 19:49:31 davem Exp $ */
   2 #ifndef __SPARC64_MMU_CONTEXT_H
   3 #define __SPARC64_MMU_CONTEXT_H
   4
   5 /* Derived heavily from Linus's Alpha/AXP ASN code... */
   6
   7 #ifndef __ASSEMBLY__
   8
   9 #include <linux/spinlock.h>
  10 #include <asm/system.h>
  11 #include <asm/spitfire.h>
  12
  13 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  14 {
  15 }
  16
  17 extern spinlock_t ctx_alloc_lock;
  18 extern unsigned long tlb_context_cache;
  19 extern unsigned long mmu_context_bmap[];
  20
  21 extern void get_new_mmu_context(struct mm_struct *mm);
  22 #ifdef CONFIG_SMP
  23 extern void smp_new_mmu_context_version(void);
  24 #else
  25 #define smp_new_mmu_context_version() do { } while (0)
  26 #endif
  27
  28 extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
  29 extern void destroy_context(struct mm_struct *mm);
  30
  31 extern void __tsb_context_switch(unsigned long pgd_pa,
  32                                  unsigned long tsb_reg,
  33                                  unsigned long tsb_vaddr,
  34                                  unsigned long tsb_pte,
  35                                  unsigned long tsb_descr_pa);
  36
  37 static inline void tsb_context_switch(struct mm_struct *mm)
  38 {
  39         __tsb_context_switch(__pa(mm->pgd), mm->context.tsb_reg_val,
  40                              mm->context.tsb_map_vaddr,
  41                              mm->context.tsb_map_pte,
  42                              __pa(&mm->context.tsb_descr));
  43 }
  44
  45 extern void tsb_grow(struct mm_struct *mm, unsigned long mm_rss);
  46 #ifdef CONFIG_SMP
  47 extern void smp_tsb_sync(struct mm_struct *mm);
  48 #else
  49 #define smp_tsb_sync(__mm) do { } while (0)
  50 #endif
  51
  52 /* Set MMU context in the actual hardware. */
  53 #define load_secondary_context(__mm) \
  54         __asm__ __volatile__( \
  55         "\n661: stxa            %0, [%1] %2\n" \
  56         "       .section        .sun4v_1insn_patch, \"ax\"\n" \
  57         "       .word           661b\n" \
  58         "       stxa            %0, [%1] %3\n" \
  59         "       .previous\n" \
  60         "       flush           %%g6\n" \
  61         : /* No outputs */ \
  62         : "r" (CTX_HWBITS((__mm)->context)), \
  63           "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
  64
  65 extern void __flush_tlb_mm(unsigned long, unsigned long);
  66
  67 /* Switch the current MM context.  Interrupts are disabled.  */
  68 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
  69 {
  70         unsigned long ctx_valid, flags;
  71         int cpu;
  72
  73         spin_lock_irqsave(&mm->context.lock, flags);
  74         ctx_valid = CTX_VALID(mm->context);
  75         if (!ctx_valid)
  76                 get_new_mmu_context(mm);
  77
  78         /* We have to be extremely careful here or else we will miss
  79          * a TSB grow if we switch back and forth between a kernel
  80          * thread and an address space which has it's TSB size increased
  81          * on another processor.
  82          *
  83          * It is possible to play some games in order to optimize the
  84          * switch, but the safest thing to do is to unconditionally
  85          * perform the secondary context load and the TSB context switch.
  86          *
  87          * For reference the bad case is, for address space "A":
  88          *
  89          *              CPU 0                   CPU 1
  90          *      run address space A
  91          *      set cpu0's bits in cpu_vm_mask
  92          *      switch to kernel thread, borrow
  93          *      address space A via entry_lazy_tlb
  94          *                                      run address space A
  95          *                                      set cpu1's bit in cpu_vm_mask
  96          *                                      flush_tlb_pending()
  97          *                                      reset cpu_vm_mask to just cpu1
  98          *                                      TSB grow
  99          *      run address space A
 100          *      context was valid, so skip
 101          *      TSB context switch
 102          *
 103          * At that point cpu0 continues to use a stale TSB, the one from
 104          * before the TSB grow performed on cpu1.  cpu1 did not cross-call
 105          * cpu0 to update it's TSB because at that point the cpu_vm_mask
 106          * only had cpu1 set in it.
 107          */
 108         load_secondary_context(mm);
 109         tsb_context_switch(mm);
 110
 111         /* Any time a processor runs a context on an address space
 112          * for the first time, we must flush that context out of the
 113          * local TLB.
 114          */
 115         cpu = smp_processor_id();
 116         if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
 117                 cpu_set(cpu, mm->cpu_vm_mask);
 118                 __flush_tlb_mm(CTX_HWBITS(mm->context),
 119                                SECONDARY_CONTEXT);
 120         }
 121         spin_unlock_irqrestore(&mm->context.lock, flags);
 122 }
 123
 124 #define deactivate_mm(tsk,mm)   do { } while (0)
 125
 126 /* Activate a new MM instance for the current task. */
 127 static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
 128 {
 129         unsigned long flags;
 130         int cpu;
 131
 132         spin_lock_irqsave(&mm->context.lock, flags);
 133         if (!CTX_VALID(mm->context))
 134                 get_new_mmu_context(mm);
 135         cpu = smp_processor_id();
 136         if (!cpu_isset(cpu, mm->cpu_vm_mask))
 137                 cpu_set(cpu, mm->cpu_vm_mask);
 138
 139         load_secondary_context(mm);
 140         __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
 141         tsb_context_switch(mm);
 142         spin_unlock_irqrestore(&mm->context.lock, flags);
 143 }
 144
 145 #endif /* !(__ASSEMBLY__) */
 146
 147 #endif /* !(__SPARC64_MMU_CONTEXT_H) */