include/asm-x86/apicdef.h

   1 #ifndef ASM_X86__APICDEF_H
   2 #define ASM_X86__APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define APIC_ID         0x20
  14
  15 #define APIC_LVR        0x30
  16 #define         APIC_LVR_MASK           0xFF00FF
  17 #define         GET_APIC_VERSION(x)     ((x) & 0xFFu)
  18 #define         GET_APIC_MAXLVT(x)      (((x) >> 16) & 0xFFu)
  19 #ifdef CONFIG_X86_32
  20 #  define       APIC_INTEGRATED(x)      ((x) & 0xF0u)
  21 #else
  22 #  define       APIC_INTEGRATED(x)      (1)
  23 #endif
  24 #define         APIC_XAPIC(x)           ((x) >= 0x14)
  25 #define APIC_TASKPRI    0x80
  26 #define         APIC_TPRI_MASK          0xFFu
  27 #define APIC_ARBPRI     0x90
  28 #define         APIC_ARBPRI_MASK        0xFFu
  29 #define APIC_PROCPRI    0xA0
  30 #define APIC_EOI        0xB0
  31 #define         APIC_EIO_ACK            0x0
  32 #define APIC_RRR        0xC0
  33 #define APIC_LDR        0xD0
  34 #define         APIC_LDR_MASK           (0xFFu << 24)
  35 #define         GET_APIC_LOGICAL_ID(x)  (((x) >> 24) & 0xFFu)
  36 #define         SET_APIC_LOGICAL_ID(x)  (((x) << 24))
  37 #define         APIC_ALL_CPUS           0xFFu
  38 #define APIC_DFR        0xE0
  39 #define         APIC_DFR_CLUSTER                0x0FFFFFFFul
  40 #define         APIC_DFR_FLAT                   0xFFFFFFFFul
  41 #define APIC_SPIV       0xF0
  42 #define         APIC_SPIV_FOCUS_DISABLED        (1 << 9)
  43 #define         APIC_SPIV_APIC_ENABLED          (1 << 8)
  44 #define APIC_ISR        0x100
  45 #define APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
  46 #define APIC_TMR        0x180
  47 #define APIC_IRR        0x200
  48 #define APIC_ESR        0x280
  49 #define         APIC_ESR_SEND_CS        0x00001
  50 #define         APIC_ESR_RECV_CS        0x00002
  51 #define         APIC_ESR_SEND_ACC       0x00004
  52 #define         APIC_ESR_RECV_ACC       0x00008
  53 #define         APIC_ESR_SENDILL        0x00020
  54 #define         APIC_ESR_RECVILL        0x00040
  55 #define         APIC_ESR_ILLREGA        0x00080
  56 #define APIC_ICR        0x300
  57 #define         APIC_DEST_SELF          0x40000
  58 #define         APIC_DEST_ALLINC        0x80000
  59 #define         APIC_DEST_ALLBUT        0xC0000
  60 #define         APIC_ICR_RR_MASK        0x30000
  61 #define         APIC_ICR_RR_INVALID     0x00000
  62 #define         APIC_ICR_RR_INPROG      0x10000
  63 #define         APIC_ICR_RR_VALID       0x20000
  64 #define         APIC_INT_LEVELTRIG      0x08000
  65 #define         APIC_INT_ASSERT         0x04000
  66 #define         APIC_ICR_BUSY           0x01000
  67 #define         APIC_DEST_LOGICAL       0x00800
  68 #define         APIC_DEST_PHYSICAL      0x00000
  69 #define         APIC_DM_FIXED           0x00000
  70 #define         APIC_DM_LOWEST          0x00100
  71 #define         APIC_DM_SMI             0x00200
  72 #define         APIC_DM_REMRD           0x00300
  73 #define         APIC_DM_NMI             0x00400
  74 #define         APIC_DM_INIT            0x00500
  75 #define         APIC_DM_STARTUP         0x00600
  76 #define         APIC_DM_EXTINT          0x00700
  77 #define         APIC_VECTOR_MASK        0x000FF
  78 #define APIC_ICR2       0x310
  79 #define         GET_APIC_DEST_FIELD(x)  (((x) >> 24) & 0xFF)
  80 #define         SET_APIC_DEST_FIELD(x)  ((x) << 24)
  81 #define APIC_LVTT       0x320
  82 #define APIC_LVTTHMR    0x330
  83 #define APIC_LVTPC      0x340
  84 #define APIC_LVT0       0x350
  85 #define         APIC_LVT_TIMER_BASE_MASK        (0x3 << 18)
  86 #define         GET_APIC_TIMER_BASE(x)          (((x) >> 18) & 0x3)
  87 #define         SET_APIC_TIMER_BASE(x)          (((x) << 18))
  88 #define         APIC_TIMER_BASE_CLKIN           0x0
  89 #define         APIC_TIMER_BASE_TMBASE          0x1
  90 #define         APIC_TIMER_BASE_DIV             0x2
  91 #define         APIC_LVT_TIMER_PERIODIC         (1 << 17)
  92 #define         APIC_LVT_MASKED                 (1 << 16)
  93 #define         APIC_LVT_LEVEL_TRIGGER          (1 << 15)
  94 #define         APIC_LVT_REMOTE_IRR             (1 << 14)
  95 #define         APIC_INPUT_POLARITY             (1 << 13)
  96 #define         APIC_SEND_PENDING               (1 << 12)
  97 #define         APIC_MODE_MASK                  0x700
  98 #define         GET_APIC_DELIVERY_MODE(x)       (((x) >> 8) & 0x7)
  99 #define         SET_APIC_DELIVERY_MODE(x, y)    (((x) & ~0x700) | ((y) << 8))
 100 #define                 APIC_MODE_FIXED         0x0
 101 #define                 APIC_MODE_NMI           0x4
 102 #define                 APIC_MODE_EXTINT        0x7
 103 #define APIC_LVT1       0x360
 104 #define APIC_LVTERR     0x370
 105 #define APIC_TMICT      0x380
 106 #define APIC_TMCCT      0x390
 107 #define APIC_TDCR       0x3E0
 108 #define APIC_SELF_IPI   0x3F0
 109 #define         APIC_TDR_DIV_TMBASE     (1 << 2)
 110 #define         APIC_TDR_DIV_1          0xB
 111 #define         APIC_TDR_DIV_2          0x0
 112 #define         APIC_TDR_DIV_4          0x1
 113 #define         APIC_TDR_DIV_8          0x2
 114 #define         APIC_TDR_DIV_16         0x3
 115 #define         APIC_TDR_DIV_32         0x8
 116 #define         APIC_TDR_DIV_64         0x9
 117 #define         APIC_TDR_DIV_128        0xA
 118 #define APIC_EILVT0     0x500
 119 #define         APIC_EILVT_NR_AMD_K8    1       /* # of extended interrupts */
 120 #define         APIC_EILVT_NR_AMD_10H   4
 121 #define         APIC_EILVT_LVTOFF(x)    (((x) >> 4) & 0xF)
 122 #define         APIC_EILVT_MSG_FIX      0x0
 123 #define         APIC_EILVT_MSG_SMI      0x2
 124 #define         APIC_EILVT_MSG_NMI      0x4
 125 #define         APIC_EILVT_MSG_EXT      0x7
 126 #define         APIC_EILVT_MASKED       (1 << 16)
 127 #define APIC_EILVT1     0x510
 128 #define APIC_EILVT2     0x520
 129 #define APIC_EILVT3     0x530
 130
 131 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 132 #define APIC_BASE_MSR   0x800
 133 #define X2APIC_ENABLE   (1UL << 10)
 134
 135 #ifdef CONFIG_X86_32
 136 # define MAX_IO_APICS 64
 137 #else
 138 # define MAX_IO_APICS 128
 139 # define MAX_LOCAL_APIC 32768
 140 #endif
 141
 142 /*
 143  * All x86-64 systems are xAPIC compatible.
 144  * In the following, "apicid" is a physical APIC ID.
 145  */
 146 #define XAPIC_DEST_CPUS_SHIFT   4
 147 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
 148 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
 149 #define APIC_CLUSTER(apicid)    ((apicid) & XAPIC_DEST_CLUSTER_MASK)
 150 #define APIC_CLUSTERID(apicid)  (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
 151 #define APIC_CPUID(apicid)      ((apicid) & XAPIC_DEST_CPUS_MASK)
 152 #define NUM_APIC_CLUSTERS       ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
 153
 154 /*
 155  * the local APIC register structure, memory mapped. Not terribly well
 156  * tested, but we might eventually use this one in the future - the
 157  * problem why we cannot use it right now is the P5 APIC, it has an
 158  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 159  */
 160 #define u32 unsigned int
 161
 162 struct local_apic {
 163
 164 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 165
 166 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 167
 168 /*020*/ struct { /* APIC ID Register */
 169                 u32   __reserved_1      : 24,
 170                         phys_apic_id    :  4,
 171                         __reserved_2    :  4;
 172                 u32 __reserved[3];
 173         } id;
 174
 175 /*030*/ const
 176         struct { /* APIC Version Register */
 177                 u32   version           :  8,
 178                         __reserved_1    :  8,
 179                         max_lvt         :  8,
 180                         __reserved_2    :  8;
 181                 u32 __reserved[3];
 182         } version;
 183
 184 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 185
 186 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 187
 188 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 189
 190 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 191
 192 /*080*/ struct { /* Task Priority Register */
 193                 u32   priority  :  8,
 194                         __reserved_1    : 24;
 195                 u32 __reserved_2[3];
 196         } tpr;
 197
 198 /*090*/ const
 199         struct { /* Arbitration Priority Register */
 200                 u32   priority  :  8,
 201                         __reserved_1    : 24;
 202                 u32 __reserved_2[3];
 203         } apr;
 204
 205 /*0A0*/ const
 206         struct { /* Processor Priority Register */
 207                 u32   priority  :  8,
 208                         __reserved_1    : 24;
 209                 u32 __reserved_2[3];
 210         } ppr;
 211
 212 /*0B0*/ struct { /* End Of Interrupt Register */
 213                 u32   eoi;
 214                 u32 __reserved[3];
 215         } eoi;
 216
 217 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 218
 219 /*0D0*/ struct { /* Logical Destination Register */
 220                 u32   __reserved_1      : 24,
 221                         logical_dest    :  8;
 222                 u32 __reserved_2[3];
 223         } ldr;
 224
 225 /*0E0*/ struct { /* Destination Format Register */
 226                 u32   __reserved_1      : 28,
 227                         model           :  4;
 228                 u32 __reserved_2[3];
 229         } dfr;
 230
 231 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 232                 u32     spurious_vector :  8,
 233                         apic_enabled    :  1,
 234                         focus_cpu       :  1,
 235                         __reserved_2    : 22;
 236                 u32 __reserved_3[3];
 237         } svr;
 238
 239 /*100*/ struct { /* In Service Register */
 240 /*170*/         u32 bitfield;
 241                 u32 __reserved[3];
 242         } isr [8];
 243
 244 /*180*/ struct { /* Trigger Mode Register */
 245 /*1F0*/         u32 bitfield;
 246                 u32 __reserved[3];
 247         } tmr [8];
 248
 249 /*200*/ struct { /* Interrupt Request Register */
 250 /*270*/         u32 bitfield;
 251                 u32 __reserved[3];
 252         } irr [8];
 253
 254 /*280*/ union { /* Error Status Register */
 255                 struct {
 256                         u32   send_cs_error                     :  1,
 257                                 receive_cs_error                :  1,
 258                                 send_accept_error               :  1,
 259                                 receive_accept_error            :  1,
 260                                 __reserved_1                    :  1,
 261                                 send_illegal_vector             :  1,
 262                                 receive_illegal_vector          :  1,
 263                                 illegal_register_address        :  1,
 264                                 __reserved_2                    : 24;
 265                         u32 __reserved_3[3];
 266                 } error_bits;
 267                 struct {
 268                         u32 errors;
 269                         u32 __reserved_3[3];
 270                 } all_errors;
 271         } esr;
 272
 273 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 274
 275 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 276
 277 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 278
 279 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 280
 281 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 282
 283 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 284
 285 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 286
 287 /*300*/ struct { /* Interrupt Command Register 1 */
 288                 u32   vector                    :  8,
 289                         delivery_mode           :  3,
 290                         destination_mode        :  1,
 291                         delivery_status         :  1,
 292                         __reserved_1            :  1,
 293                         level                   :  1,
 294                         trigger                 :  1,
 295                         __reserved_2            :  2,
 296                         shorthand               :  2,
 297                         __reserved_3            :  12;
 298                 u32 __reserved_4[3];
 299         } icr1;
 300
 301 /*310*/ struct { /* Interrupt Command Register 2 */
 302                 union {
 303                         u32   __reserved_1      : 24,
 304                                 phys_dest       :  4,
 305                                 __reserved_2    :  4;
 306                         u32   __reserved_3      : 24,
 307                                 logical_dest    :  8;
 308                 } dest;
 309                 u32 __reserved_4[3];
 310         } icr2;
 311
 312 /*320*/ struct { /* LVT - Timer */
 313                 u32   vector            :  8,
 314                         __reserved_1    :  4,
 315                         delivery_status :  1,
 316                         __reserved_2    :  3,
 317                         mask            :  1,
 318                         timer_mode      :  1,
 319                         __reserved_3    : 14;
 320                 u32 __reserved_4[3];
 321         } lvt_timer;
 322
 323 /*330*/ struct { /* LVT - Thermal Sensor */
 324                 u32  vector             :  8,
 325                         delivery_mode   :  3,
 326                         __reserved_1    :  1,
 327                         delivery_status :  1,
 328                         __reserved_2    :  3,
 329                         mask            :  1,
 330                         __reserved_3    : 15;
 331                 u32 __reserved_4[3];
 332         } lvt_thermal;
 333
 334 /*340*/ struct { /* LVT - Performance Counter */
 335                 u32   vector            :  8,
 336                         delivery_mode   :  3,
 337                         __reserved_1    :  1,
 338                         delivery_status :  1,
 339                         __reserved_2    :  3,
 340                         mask            :  1,
 341                         __reserved_3    : 15;
 342                 u32 __reserved_4[3];
 343         } lvt_pc;
 344
 345 /*350*/ struct { /* LVT - LINT0 */
 346                 u32   vector            :  8,
 347                         delivery_mode   :  3,
 348                         __reserved_1    :  1,
 349                         delivery_status :  1,
 350                         polarity        :  1,
 351                         remote_irr      :  1,
 352                         trigger         :  1,
 353                         mask            :  1,
 354                         __reserved_2    : 15;
 355                 u32 __reserved_3[3];
 356         } lvt_lint0;
 357
 358 /*360*/ struct { /* LVT - LINT1 */
 359                 u32   vector            :  8,
 360                         delivery_mode   :  3,
 361                         __reserved_1    :  1,
 362                         delivery_status :  1,
 363                         polarity        :  1,
 364                         remote_irr      :  1,
 365                         trigger         :  1,
 366                         mask            :  1,
 367                         __reserved_2    : 15;
 368                 u32 __reserved_3[3];
 369         } lvt_lint1;
 370
 371 /*370*/ struct { /* LVT - Error */
 372                 u32   vector            :  8,
 373                         __reserved_1    :  4,
 374                         delivery_status :  1,
 375                         __reserved_2    :  3,
 376                         mask            :  1,
 377                         __reserved_3    : 15;
 378                 u32 __reserved_4[3];
 379         } lvt_error;
 380
 381 /*380*/ struct { /* Timer Initial Count Register */
 382                 u32   initial_count;
 383                 u32 __reserved_2[3];
 384         } timer_icr;
 385
 386 /*390*/ const
 387         struct { /* Timer Current Count Register */
 388                 u32   curr_count;
 389                 u32 __reserved_2[3];
 390         } timer_ccr;
 391
 392 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 393
 394 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 395
 396 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 397
 398 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 399
 400 /*3E0*/ struct { /* Timer Divide Configuration Register */
 401                 u32   divisor           :  4,
 402                         __reserved_1    : 28;
 403                 u32 __reserved_2[3];
 404         } timer_dcr;
 405
 406 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 407
 408 } __attribute__ ((packed));
 409
 410 #undef u32
 411
 412 #ifdef CONFIG_X86_32
 413  #define BAD_APICID 0xFFu
 414 #else
 415  #define BAD_APICID 0xFFFFu
 416 #endif
 417 #endif /* ASM_X86__APICDEF_H */