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1 #ifndef __ASM_X86_MSR_H_
2 #define __ASM_X86_MSR_H_
3
4 #include <asm/msr-index.h>
5
6 #ifndef __ASSEMBLY__
7 # include <linux/types.h>
8 #endif
9
10 #ifdef __KERNEL__
11 #ifndef __ASSEMBLY__
12
13 #include <asm/asm.h>
14 #include <asm/errno.h>
15
16 static inline unsigned long long native_read_tscp(unsigned int *aux)
17 {
18 unsigned long low, high;
19 asm volatile(".byte 0x0f,0x01,0xf9"
20 : "=a" (low), "=d" (high), "=c" (*aux));
21 return low | ((u64)high << 32);
22 }
23
24 /*
25 * i386 calling convention returns 64-bit value in edx:eax, while
26 * x86_64 returns at rax. Also, the "A" constraint does not really
27 * mean rdx:rax in x86_64, so we need specialized behaviour for each
28 * architecture
29 */
30 #ifdef CONFIG_X86_64
31 #define DECLARE_ARGS(val, low, high) unsigned low, high
32 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
33 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
34 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
35 #else
36 #define DECLARE_ARGS(val, low, high) unsigned long long val
37 #define EAX_EDX_VAL(val, low, high) (val)
38 #define EAX_EDX_ARGS(val, low, high) "A" (val)
39 #define EAX_EDX_RET(val, low, high) "=A" (val)
40 #endif
41
42 static inline unsigned long long native_read_msr(unsigned int msr)
43 {
44 DECLARE_ARGS(val, low, high);
45
46 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
47 return EAX_EDX_VAL(val, low, high);
48 }
49
50 static inline unsigned long long native_read_msr_safe(unsigned int msr,
51 int *err)
52 {
53 DECLARE_ARGS(val, low, high);
54
55 asm volatile("2: rdmsr ; xor %0,%0\n"
56 "1:\n\t"
57 ".section .fixup,\"ax\"\n\t"
58 "3: mov %3,%0 ; jmp 1b\n\t"
59 ".previous\n\t"
60 _ASM_EXTABLE(2b, 3b)
61 : "=r" (*err), EAX_EDX_RET(val, low, high)
62 : "c" (msr), "i" (-EFAULT));
63 return EAX_EDX_VAL(val, low, high);
64 }
65
66 static inline void native_write_msr(unsigned int msr,
67 unsigned low, unsigned high)
68 {
69 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
70 }
71
72 static inline int native_write_msr_safe(unsigned int msr,
73 unsigned low, unsigned high)
74 {
75 int err;
76 asm volatile("2: wrmsr ; xor %0,%0\n"
77 "1:\n\t"
78 ".section .fixup,\"ax\"\n\t"
79 "3: mov %4,%0 ; jmp 1b\n\t"
80 ".previous\n\t"
81 _ASM_EXTABLE(2b, 3b)
82 : "=a" (err)
83 : "c" (msr), "0" (low), "d" (high),
84 "i" (-EFAULT)
85 : "memory");
86 return err;
87 }
88
89 extern unsigned long long native_read_tsc(void);
90
91 static __always_inline unsigned long long __native_read_tsc(void)
92 {
93 DECLARE_ARGS(val, low, high);
94
95 rdtsc_barrier();
96 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
97 rdtsc_barrier();
98
99 return EAX_EDX_VAL(val, low, high);
100 }
101
102 static inline unsigned long long native_read_pmc(int counter)
103 {
104 DECLARE_ARGS(val, low, high);
105
106 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
107 return EAX_EDX_VAL(val, low, high);
108 }
109
110 #ifdef CONFIG_PARAVIRT
111 #include <asm/paravirt.h>
112 #else
113 #include <linux/errno.h>
114 /*
115 * Access to machine-specific registers (available on 586 and better only)
116 * Note: the rd* operations modify the parameters directly (without using
117 * pointer indirection), this allows gcc to optimize better
118 */
119
120 #define rdmsr(msr, val1, val2) \
121 do { \
122 u64 __val = native_read_msr((msr)); \
123 (val1) = (u32)__val; \
124 (val2) = (u32)(__val >> 32); \
125 } while (0)
126
127 static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
128 {
129 native_write_msr(msr, low, high);
130 }
131
132 #define rdmsrl(msr, val) \
133 ((val) = native_read_msr((msr)))
134
135 #define wrmsrl(msr, val) \
136 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
137
138 /* wrmsr with exception handling */
139 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
140 {
141 return native_write_msr_safe(msr, low, high);
142 }
143
144 /* rdmsr with exception handling */
145 #define rdmsr_safe(msr, p1, p2) \
146 ({ \
147 int __err; \
148 u64 __val = native_read_msr_safe((msr), &__err); \
149 (*p1) = (u32)__val; \
150 (*p2) = (u32)(__val >> 32); \
151 __err; \
152 })
153
154 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
155 {
156 int err;
157
158 *p = native_read_msr_safe(msr, &err);
159 return err;
160 }
161
162 #define rdtscl(low) \
163 ((low) = (u32)native_read_tsc())
164
165 #define rdtscll(val) \
166 ((val) = native_read_tsc())
167
168 #define rdpmc(counter, low, high) \
169 do { \
170 u64 _l = native_read_pmc((counter)); \
171 (low) = (u32)_l; \
172 (high) = (u32)(_l >> 32); \
173 } while (0)
174
175 #define rdtscp(low, high, aux) \
176 do { \
177 unsigned long long _val = native_read_tscp(&(aux)); \
178 (low) = (u32)_val; \
179 (high) = (u32)(_val >> 32); \
180 } while (0)
181
182 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
183
184 #endif /* !CONFIG_PARAVIRT */
185
186
187 #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \
188 (u32)((val) >> 32))
189
190 #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2))
191
192 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
193
194 #ifdef CONFIG_SMP
195 void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
196 void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
197 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
198
199 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
200 #else /* CONFIG_SMP */
201 static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
202 {
203 rdmsr(msr_no, *l, *h);
204 }
205 static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
206 {
207 wrmsr(msr_no, l, h);
208 }
209 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
210 u32 *l, u32 *h)
211 {
212 return rdmsr_safe(msr_no, l, h);
213 }
214 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
215 {
216 return wrmsr_safe(msr_no, l, h);
217 }
218 #endif /* CONFIG_SMP */
219 #endif /* __ASSEMBLY__ */
220 #endif /* __KERNEL__ */
221
222
223 #endif