include/asm-x86/pgtable_32.h

   1 #ifndef _I386_PGTABLE_H
   2 #define _I386_PGTABLE_H
   3
   4
   5 /*
   6  * The Linux memory management assumes a three-level page table setup. On
   7  * the i386, we use that, but "fold" the mid level into the top-level page
   8  * table, so that we physically have the same two-level page table as the
   9  * i386 mmu expects.
  10  *
  11  * This file contains the functions and defines necessary to modify and use
  12  * the i386 page table tree.
  13  */
  14 #ifndef __ASSEMBLY__
  15 #include <asm/processor.h>
  16 #include <asm/fixmap.h>
  17 #include <linux/threads.h>
  18 #include <asm/paravirt.h>
  19
  20 #include <linux/bitops.h>
  21 #include <linux/slab.h>
  22 #include <linux/list.h>
  23 #include <linux/spinlock.h>
  24
  25 struct mm_struct;
  26 struct vm_area_struct;
  27
  28 extern pgd_t swapper_pg_dir[1024];
  29
  30 static inline void pgtable_cache_init(void) { }
  31 static inline void check_pgt_cache(void) { }
  32 void paging_init(void);
  33
  34 extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t);
  35
  36 /*
  37  * The Linux x86 paging architecture is 'compile-time dual-mode', it
  38  * implements both the traditional 2-level x86 page tables and the
  39  * newer 3-level PAE-mode page tables.
  40  */
  41 #ifdef CONFIG_X86_PAE
  42 # include <asm/pgtable-3level-defs.h>
  43 # define PMD_SIZE       (1UL << PMD_SHIFT)
  44 # define PMD_MASK       (~(PMD_SIZE - 1))
  45 #else
  46 # include <asm/pgtable-2level-defs.h>
  47 #endif
  48
  49 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  50 #define PGDIR_MASK      (~(PGDIR_SIZE - 1))
  51
  52 /* Just any arbitrary offset to the start of the vmalloc VM area: the
  53  * current 8MB value just means that there will be a 8MB "hole" after the
  54  * physical memory until the kernel virtual memory starts.  That means that
  55  * any out-of-bounds memory accesses will hopefully be caught.
  56  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  57  * area for the same reason. ;)
  58  */
  59 #define VMALLOC_OFFSET  (8 * 1024 * 1024)
  60 #define VMALLOC_START   (((unsigned long)high_memory + 2 * VMALLOC_OFFSET - 1) \
  61                          & ~(VMALLOC_OFFSET - 1))
  62 #ifdef CONFIG_X86_PAE
  63 #define LAST_PKMAP 512
  64 #else
  65 #define LAST_PKMAP 1024
  66 #endif
  67
  68 #define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE * (LAST_PKMAP + 1)) \
  69                     & PMD_MASK)
  70
  71 #ifdef CONFIG_HIGHMEM
  72 # define VMALLOC_END    (PKMAP_BASE - 2 * PAGE_SIZE)
  73 #else
  74 # define VMALLOC_END    (FIXADDR_START - 2 * PAGE_SIZE)
  75 #endif
  76
  77 /*
  78  * Define this if things work differently on an i386 and an i486:
  79  * it will (on an i486) warn about kernel memory accesses that are
  80  * done without a 'access_ok(VERIFY_WRITE,..)'
  81  */
  82 #undef TEST_ACCESS_OK
  83
  84 /* The boot page tables (all created as a single array) */
  85 extern unsigned long pg0[];
  86
  87 #define pte_present(x)  ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
  88
  89 /* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
  90 #define pmd_none(x)     (!(unsigned long)pmd_val((x)))
  91 #define pmd_present(x)  (pmd_val((x)) & _PAGE_PRESENT)
  92 #define pmd_bad(x) ((pmd_val(x) & (PTE_FLAGS_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
  93
  94 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
  95
  96 #ifdef CONFIG_X86_PAE
  97 # include <asm/pgtable-3level.h>
  98 #else
  99 # include <asm/pgtable-2level.h>
 100 #endif
 101
 102 /*
 103  * Macro to mark a page protection value as "uncacheable".
 104  * On processors which do not support it, this is a no-op.
 105  */
 106 #define pgprot_noncached(prot)                                  \
 107         ((boot_cpu_data.x86 > 3)                                \
 108          ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) \
 109          : (prot))
 110
 111 /*
 112  * Conversion functions: convert a page and protection to a page entry,
 113  * and a page entry and page directory to the page they refer to.
 114  */
 115 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 116
 117
 118 static inline int pud_large(pud_t pud) { return 0; }
 119
 120 /*
 121  * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
 122  *
 123  * this macro returns the index of the entry in the pmd page which would
 124  * control the given virtual address
 125  */
 126 #define pmd_index(address)                              \
 127         (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 128
 129 /*
 130  * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
 131  *
 132  * this macro returns the index of the entry in the pte page which would
 133  * control the given virtual address
 134  */
 135 #define pte_index(address)                                      \
 136         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 137 #define pte_offset_kernel(dir, address)                         \
 138         ((pte_t *)pmd_page_vaddr(*(dir)) +  pte_index((address)))
 139
 140 #define pmd_page(pmd) (pfn_to_page(pmd_val((pmd)) >> PAGE_SHIFT))
 141
 142 #define pmd_page_vaddr(pmd)                                     \
 143         ((unsigned long)__va(pmd_val((pmd)) & PTE_PFN_MASK))
 144
 145 #if defined(CONFIG_HIGHPTE)
 146 #define pte_offset_map(dir, address)                                    \
 147         ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE0) +          \
 148          pte_index((address)))
 149 #define pte_offset_map_nested(dir, address)                             \
 150         ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE1) +          \
 151          pte_index((address)))
 152 #define pte_unmap(pte) kunmap_atomic((pte), KM_PTE0)
 153 #define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1)
 154 #else
 155 #define pte_offset_map(dir, address)                                    \
 156         ((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
 157 #define pte_offset_map_nested(dir, address) pte_offset_map((dir), (address))
 158 #define pte_unmap(pte) do { } while (0)
 159 #define pte_unmap_nested(pte) do { } while (0)
 160 #endif
 161
 162 /* Clear a kernel PTE and flush it from the TLB */
 163 #define kpte_clear_flush(ptep, vaddr)           \
 164 do {                                            \
 165         pte_clear(&init_mm, (vaddr), (ptep));   \
 166         __flush_tlb_one((vaddr));               \
 167 } while (0)
 168
 169 /*
 170  * The i386 doesn't have any external MMU info: the kernel page
 171  * tables contain all the necessary information.
 172  */
 173 #define update_mmu_cache(vma, address, pte) do { } while (0)
 174
 175 #endif /* !__ASSEMBLY__ */
 176
 177 /*
 178  * kern_addr_valid() is (1) for FLATMEM and (0) for
 179  * SPARSEMEM and DISCONTIGMEM
 180  */
 181 #ifdef CONFIG_FLATMEM
 182 #define kern_addr_valid(addr)   (1)
 183 #else
 184 #define kern_addr_valid(kaddr)  (0)
 185 #endif
 186
 187 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
 188         remap_pfn_range(vma, vaddr, pfn, size, prot)
 189
 190 #endif /* _I386_PGTABLE_H */