include/asm-x86/processor_64.h

   1 /*
   2  * Copyright (C) 1994 Linus Torvalds
   3  */
   4
   5 #ifndef __ASM_X86_64_PROCESSOR_H
   6 #define __ASM_X86_64_PROCESSOR_H
   7
   8 #include <asm/segment.h>
   9 #include <asm/page.h>
  10 #include <asm/types.h>
  11 #include <asm/sigcontext.h>
  12 #include <asm/cpufeature.h>
  13 #include <linux/threads.h>
  14 #include <asm/msr.h>
  15 #include <asm/current.h>
  16 #include <asm/system.h>
  17 #include <asm/mmsegment.h>
  18 #include <asm/percpu.h>
  19 #include <linux/personality.h>
  20 #include <linux/cpumask.h>
  21 #include <asm/desc_defs.h>
  22
  23 static inline int desc_empty(const void *ptr)
  24 {
  25         const u32 *desc = ptr;
  26         return !(desc[0] | desc[1]);
  27 }
  28
  29 /*
  30  * Default implementation of macro that returns current
  31  * instruction pointer ("program counter").
  32  */
  33 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
  34
  35 /*
  36  *  CPU type and hardware bug flags. Kept separately for each CPU.
  37  */
  38
  39 struct cpuinfo_x86 {
  40         __u8    x86;            /* CPU family */
  41         __u8    x86_vendor;     /* CPU vendor */
  42         __u8    x86_model;
  43         __u8    x86_mask;
  44         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  45         __u32   x86_capability[NCAPINTS];
  46         char    x86_vendor_id[16];
  47         char    x86_model_id[64];
  48         int     x86_cache_size;  /* in KB */
  49         int     x86_clflush_size;
  50         int     x86_cache_alignment;
  51         int     x86_tlbsize;    /* number of 4K pages in DTLB/ITLB combined(in pages)*/
  52         __u8    x86_virt_bits, x86_phys_bits;
  53         __u8    x86_max_cores;  /* cpuid returned max cores value */
  54         __u8    x86_coreid_bits; /* cpuid returned core id bits */
  55         __u32   x86_power;
  56         __u32   extended_cpuid_level;   /* Max extended CPUID function supported */
  57         unsigned long loops_per_jiffy;
  58 #ifdef CONFIG_SMP
  59         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  60 #endif
  61         __u8    apicid;
  62 #ifdef CONFIG_SMP
  63         __u8    booted_cores;   /* number of cores as seen by OS */
  64         __u8    phys_proc_id;   /* Physical Processor id. */
  65         __u8    cpu_core_id;    /* Core id. */
  66         __u8    cpu_index;      /* index into per_cpu list */
  67 #endif
  68 } ____cacheline_aligned;
  69
  70 #define X86_VENDOR_INTEL 0
  71 #define X86_VENDOR_CYRIX 1
  72 #define X86_VENDOR_AMD 2
  73 #define X86_VENDOR_UMC 3
  74 #define X86_VENDOR_NEXGEN 4
  75 #define X86_VENDOR_CENTAUR 5
  76 #define X86_VENDOR_TRANSMETA 7
  77 #define X86_VENDOR_NUM 8
  78 #define X86_VENDOR_UNKNOWN 0xff
  79
  80 #ifdef CONFIG_SMP
  81 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
  82 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
  83 #define current_cpu_data        cpu_data(smp_processor_id())
  84 #else
  85 #define cpu_data(cpu)           boot_cpu_data
  86 #define current_cpu_data        boot_cpu_data
  87 #endif
  88
  89 extern char ignore_irq13;
  90
  91 extern void identify_cpu(struct cpuinfo_x86 *);
  92 extern void print_cpu_info(struct cpuinfo_x86 *);
  93 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
  94 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
  95 extern unsigned short num_cache_leaves;
  96
  97 /*
  98  * Save the cr4 feature set we're using (ie
  99  * Pentium 4MB enable and PPro Global page
 100  * enable), so that any CPU's that boot up
 101  * after us can get the correct flags.
 102  */
 103 extern unsigned long mmu_cr4_features;
 104
 105 static inline void set_in_cr4 (unsigned long mask)
 106 {
 107         mmu_cr4_features |= mask;
 108         __asm__("movq %%cr4,%%rax\n\t"
 109                 "orq %0,%%rax\n\t"
 110                 "movq %%rax,%%cr4\n"
 111                 : : "irg" (mask)
 112                 :"ax");
 113 }
 114
 115 static inline void clear_in_cr4 (unsigned long mask)
 116 {
 117         mmu_cr4_features &= ~mask;
 118         __asm__("movq %%cr4,%%rax\n\t"
 119                 "andq %0,%%rax\n\t"
 120                 "movq %%rax,%%cr4\n"
 121                 : : "irg" (~mask)
 122                 :"ax");
 123 }
 124
 125
 126 /*
 127  * User space process size. 47bits minus one guard page.
 128  */
 129 #define TASK_SIZE64     (0x800000000000UL - 4096)
 130
 131 /* This decides where the kernel will search for a free chunk of vm
 132  * space during mmap's.
 133  */
 134 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
 135
 136 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
 137 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
 138
 139 #define TASK_UNMAPPED_BASE      PAGE_ALIGN(TASK_SIZE/3)
 140
 141 /*
 142  * Size of io_bitmap.
 143  */
 144 #define IO_BITMAP_BITS  65536
 145 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 146 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 147 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 148 #define INVALID_IO_BITMAP_OFFSET 0x8000
 149
 150 struct i387_fxsave_struct {
 151         u16     cwd;
 152         u16     swd;
 153         u16     twd;
 154         u16     fop;
 155         u64     rip;
 156         u64     rdp;
 157         u32     mxcsr;
 158         u32     mxcsr_mask;
 159         u32     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 160         u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 256 bytes */
 161         u32     padding[24];
 162 } __attribute__ ((aligned (16)));
 163
 164 union i387_union {
 165         struct i387_fxsave_struct       fxsave;
 166 };
 167
 168 struct tss_struct {
 169         u32 reserved1;
 170         u64 sp0;
 171         u64 sp1;
 172         u64 sp2;
 173         u64 reserved2;
 174         u64 ist[7];
 175         u32 reserved3;
 176         u32 reserved4;
 177         u16 reserved5;
 178         u16 io_bitmap_base;
 179         /*
 180          * The extra 1 is there because the CPU will access an
 181          * additional byte beyond the end of the IO permission
 182          * bitmap. The extra byte must be all 1 bits, and must
 183          * be within the limit. Thus we have:
 184          *
 185          * 128 bytes, the bitmap itself, for ports 0..0x3ff
 186          * 8 bytes, for an extra "long" of ~0UL
 187          */
 188         unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
 189 } __attribute__((packed)) ____cacheline_aligned;
 190
 191
 192 extern struct cpuinfo_x86 boot_cpu_data;
 193 DECLARE_PER_CPU(struct tss_struct,init_tss);
 194 /* Save the original ist values for checking stack pointers during debugging */
 195 struct orig_ist {
 196         unsigned long ist[7];
 197 };
 198 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 199
 200 #ifdef CONFIG_X86_VSMP
 201 #define ARCH_MIN_TASKALIGN      (1 << INTERNODE_CACHE_SHIFT)
 202 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
 203 #else
 204 #define ARCH_MIN_TASKALIGN      16
 205 #define ARCH_MIN_MMSTRUCT_ALIGN 0
 206 #endif
 207
 208 struct thread_struct {
 209         unsigned long   sp0;
 210         unsigned long   sp;
 211         unsigned long   usersp; /* Copy from PDA */
 212         unsigned long   fs;
 213         unsigned long   gs;
 214         unsigned short  es, ds, fsindex, gsindex;
 215 /* Hardware debugging registers */
 216         unsigned long   debugreg0;
 217         unsigned long   debugreg1;
 218         unsigned long   debugreg2;
 219         unsigned long   debugreg3;
 220         unsigned long   debugreg6;
 221         unsigned long   debugreg7;
 222 /* fault info */
 223         unsigned long   cr2, trap_no, error_code;
 224 /* floating point info */
 225         union i387_union        i387  __attribute__((aligned(16)));
 226 /* IO permissions. the bitmap could be moved into the GDT, that would make
 227    switch faster for a limited number of ioperm using tasks. -AK */
 228         int             ioperm;
 229         unsigned long   *io_bitmap_ptr;
 230         unsigned io_bitmap_max;
 231 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 232         unsigned long   debugctlmsr;
 233 /* Debug Store - if not 0 points to a DS Save Area configuration;
 234  *               goes into MSR_IA32_DS_AREA */
 235         unsigned long   ds_area_msr;
 236 /* cached TLS descriptors. */
 237         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 238 } __attribute__((aligned(16)));
 239
 240 #define INIT_THREAD  { \
 241         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 242 }
 243
 244 #define INIT_TSS  { \
 245         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 246 }
 247
 248 #define INIT_MMAP \
 249 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
 250
 251 #define start_thread(regs,new_rip,new_rsp) do { \
 252         asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0));      \
 253         load_gs_index(0);                                                       \
 254         (regs)->ip = (new_rip);                                          \
 255         (regs)->sp = (new_rsp);                                          \
 256         write_pda(oldrsp, (new_rsp));                                            \
 257         (regs)->cs = __USER_CS;                                                  \
 258         (regs)->ss = __USER_DS;                                                  \
 259         (regs)->flags = 0x200;                                                   \
 260         set_fs(USER_DS);                                                         \
 261 } while(0)
 262
 263 #define get_debugreg(var, register)                             \
 264                 __asm__("movq %%db" #register ", %0"            \
 265                         :"=r" (var))
 266 #define set_debugreg(value, register)                   \
 267                 __asm__("movq %0,%%db" #register                \
 268                         : /* no output */                       \
 269                         :"r" (value))
 270
 271 struct task_struct;
 272 struct mm_struct;
 273
 274 /* Free all resources held by a thread. */
 275 extern void release_thread(struct task_struct *);
 276
 277 /* Prepare to copy thread state - unlazy all lazy status */
 278 extern void prepare_to_copy(struct task_struct *tsk);
 279
 280 /*
 281  * create a kernel thread without removing it from tasklists
 282  */
 283 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 284
 285 /*
 286  * Return saved PC of a blocked thread.
 287  * What is this good for? it will be always the scheduler or ret_from_fork.
 288  */
 289 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
 290
 291 extern unsigned long get_wchan(struct task_struct *p);
 292 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 293 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->ip)
 294 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
 295
 296
 297 struct microcode_header {
 298         unsigned int hdrver;
 299         unsigned int rev;
 300         unsigned int date;
 301         unsigned int sig;
 302         unsigned int cksum;
 303         unsigned int ldrver;
 304         unsigned int pf;
 305         unsigned int datasize;
 306         unsigned int totalsize;
 307         unsigned int reserved[3];
 308 };
 309
 310 struct microcode {
 311         struct microcode_header hdr;
 312         unsigned int bits[0];
 313 };
 314
 315 typedef struct microcode microcode_t;
 316 typedef struct microcode_header microcode_header_t;
 317
 318 /* microcode format is extended from prescott processors */
 319 struct extended_signature {
 320         unsigned int sig;
 321         unsigned int pf;
 322         unsigned int cksum;
 323 };
 324
 325 struct extended_sigtable {
 326         unsigned int count;
 327         unsigned int cksum;
 328         unsigned int reserved[3];
 329         struct extended_signature sigs[0];
 330 };
 331
 332
 333 #if defined(CONFIG_MPSC) || defined(CONFIG_MCORE2)
 334 #define ASM_NOP1 P6_NOP1
 335 #define ASM_NOP2 P6_NOP2
 336 #define ASM_NOP3 P6_NOP3
 337 #define ASM_NOP4 P6_NOP4
 338 #define ASM_NOP5 P6_NOP5
 339 #define ASM_NOP6 P6_NOP6
 340 #define ASM_NOP7 P6_NOP7
 341 #define ASM_NOP8 P6_NOP8
 342 #else
 343 #define ASM_NOP1 K8_NOP1
 344 #define ASM_NOP2 K8_NOP2
 345 #define ASM_NOP3 K8_NOP3
 346 #define ASM_NOP4 K8_NOP4
 347 #define ASM_NOP5 K8_NOP5
 348 #define ASM_NOP6 K8_NOP6
 349 #define ASM_NOP7 K8_NOP7
 350 #define ASM_NOP8 K8_NOP8
 351 #endif
 352
 353 /* Opteron nops */
 354 #define K8_NOP1 ".byte 0x90\n"
 355 #define K8_NOP2 ".byte 0x66,0x90\n"
 356 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 357 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 358 #define K8_NOP5 K8_NOP3 K8_NOP2
 359 #define K8_NOP6 K8_NOP3 K8_NOP3
 360 #define K8_NOP7 K8_NOP4 K8_NOP3
 361 #define K8_NOP8 K8_NOP4 K8_NOP4
 362
 363 /* P6 nops */
 364 /* uses eax dependencies (Intel-recommended choice) */
 365 #define P6_NOP1 ".byte 0x90\n"
 366 #define P6_NOP2 ".byte 0x66,0x90\n"
 367 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
 368 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
 369 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
 370 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
 371 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
 372 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
 373
 374 #define ASM_NOP_MAX 8
 375
 376 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 377 static inline void rep_nop(void)
 378 {
 379         __asm__ __volatile__("rep;nop": : :"memory");
 380 }
 381
 382 /* Stop speculative execution */
 383 static inline void sync_core(void)
 384 {
 385         int tmp;
 386         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 387 }
 388
 389 #define ARCH_HAS_PREFETCHW 1
 390 static inline void prefetchw(void *x)
 391 {
 392         alternative_input("prefetcht0 (%1)",
 393                           "prefetchw (%1)",
 394                           X86_FEATURE_3DNOW,
 395                           "r" (x));
 396 }
 397
 398 #define ARCH_HAS_SPINLOCK_PREFETCH 1
 399
 400 #define spin_lock_prefetch(x)  prefetchw(x)
 401
 402 #define cpu_relax()   rep_nop()
 403
 404 static inline void __monitor(const void *eax, unsigned long ecx,
 405                 unsigned long edx)
 406 {
 407         /* "monitor %eax,%ecx,%edx;" */
 408         asm volatile(
 409                 ".byte 0x0f,0x01,0xc8;"
 410                 : :"a" (eax), "c" (ecx), "d"(edx));
 411 }
 412
 413 static inline void __mwait(unsigned long eax, unsigned long ecx)
 414 {
 415         /* "mwait %eax,%ecx;" */
 416         asm volatile(
 417                 ".byte 0x0f,0x01,0xc9;"
 418                 : :"a" (eax), "c" (ecx));
 419 }
 420
 421 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 422 {
 423         /* "mwait %eax,%ecx;" */
 424         asm volatile(
 425                 "sti; .byte 0x0f,0x01,0xc9;"
 426                 : :"a" (eax), "c" (ecx));
 427 }
 428
 429 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 430
 431 extern int force_mwait;
 432
 433 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 434
 435 #define stack_current() \
 436 ({                                                              \
 437         struct thread_info *ti;                                 \
 438         asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK));  \
 439         ti->task;                                       \
 440 })
 441
 442 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 443
 444 extern unsigned long boot_option_idle_override;
 445 /* Boot loader type from the setup header */
 446 extern int bootloader_type;
 447
 448 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 449
 450 #endif /* __ASM_X86_64_PROCESSOR_H */