include/asm-x86_64/io_apic.h

   1 #ifndef __ASM_IO_APIC_H
   2 #define __ASM_IO_APIC_H
   3
   4 #include <asm/types.h>
   5 #include <asm/mpspec.h>
   6
   7 /*
   8  * Intel IO-APIC support for SMP and UP systems.
   9  *
  10  * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
  11  */
  12
  13 #ifdef CONFIG_X86_IO_APIC
  14
  15 #ifdef CONFIG_PCI_MSI
  16 static inline int use_pci_vector(void)  {return 1;}
  17 static inline void disable_edge_ioapic_vector(unsigned int vector) { }
  18 static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
  19 static inline void end_edge_ioapic_vector (unsigned int vector) { }
  20 #define startup_level_ioapic    startup_level_ioapic_vector
  21 #define shutdown_level_ioapic   mask_IO_APIC_vector
  22 #define enable_level_ioapic     unmask_IO_APIC_vector
  23 #define disable_level_ioapic    mask_IO_APIC_vector
  24 #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
  25 #define end_level_ioapic        end_level_ioapic_vector
  26 #define set_ioapic_affinity     set_ioapic_affinity_vector
  27
  28 #define startup_edge_ioapic     startup_edge_ioapic_vector
  29 #define shutdown_edge_ioapic    disable_edge_ioapic_vector
  30 #define enable_edge_ioapic      unmask_IO_APIC_vector
  31 #define disable_edge_ioapic     disable_edge_ioapic_vector
  32 #define ack_edge_ioapic         ack_edge_ioapic_vector
  33 #define end_edge_ioapic         end_edge_ioapic_vector
  34 #else
  35 static inline int use_pci_vector(void)  {return 0;}
  36 static inline void disable_edge_ioapic_irq(unsigned int irq) { }
  37 static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
  38 static inline void end_edge_ioapic_irq (unsigned int irq) { }
  39 #define startup_level_ioapic    startup_level_ioapic_irq
  40 #define shutdown_level_ioapic   mask_IO_APIC_irq
  41 #define enable_level_ioapic     unmask_IO_APIC_irq
  42 #define disable_level_ioapic    mask_IO_APIC_irq
  43 #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
  44 #define end_level_ioapic        end_level_ioapic_irq
  45 #define set_ioapic_affinity     set_ioapic_affinity_irq
  46
  47 #define startup_edge_ioapic     startup_edge_ioapic_irq
  48 #define shutdown_edge_ioapic    disable_edge_ioapic_irq
  49 #define enable_edge_ioapic      unmask_IO_APIC_irq
  50 #define disable_edge_ioapic     disable_edge_ioapic_irq
  51 #define ack_edge_ioapic         ack_edge_ioapic_irq
  52 #define end_edge_ioapic         end_edge_ioapic_irq
  53 #endif
  54
  55 #define APIC_MISMATCH_DEBUG
  56
  57 #define IO_APIC_BASE(idx) \
  58                 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
  59                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
  60
  61 /*
  62  * The structure of the IO-APIC:
  63  */
  64 union IO_APIC_reg_00 {
  65         u32     raw;
  66         struct {
  67                 u32     __reserved_2    : 14,
  68                         LTS             :  1,
  69                         delivery_type   :  1,
  70                         __reserved_1    :  8,
  71                         ID              :  8;
  72         } __attribute__ ((packed)) bits;
  73 };
  74
  75 union IO_APIC_reg_01 {
  76         u32     raw;
  77         struct {
  78                 u32     version         :  8,
  79                 __reserved_2    :  7,
  80                 PRQ             :  1,
  81                 entries         :  8,
  82                 __reserved_1    :  8;
  83         } __attribute__ ((packed)) bits;
  84 };
  85
  86 union IO_APIC_reg_02 {
  87         u32     raw;
  88         struct {
  89                 u32     __reserved_2    : 24,
  90                 arbitration     :  4,
  91                 __reserved_1    :  4;
  92         } __attribute__ ((packed)) bits;
  93 };
  94
  95 union IO_APIC_reg_03 {
  96         u32     raw;
  97         struct {
  98                 u32     boot_DT         :  1,
  99                         __reserved_1    : 31;
 100         } __attribute__ ((packed)) bits;
 101 };
 102
 103 /*
 104  * # of IO-APICs and # of IRQ routing registers
 105  */
 106 extern int nr_ioapics;
 107 extern int nr_ioapic_registers[MAX_IO_APICS];
 108
 109 enum ioapic_irq_destination_types {
 110         dest_Fixed = 0,
 111         dest_LowestPrio = 1,
 112         dest_SMI = 2,
 113         dest__reserved_1 = 3,
 114         dest_NMI = 4,
 115         dest_INIT = 5,
 116         dest__reserved_2 = 6,
 117         dest_ExtINT = 7
 118 };
 119
 120 struct IO_APIC_route_entry {
 121         __u32   vector          :  8,
 122                 delivery_mode   :  3,   /* 000: FIXED
 123                                          * 001: lowest prio
 124                                          * 111: ExtINT
 125                                          */
 126                 dest_mode       :  1,   /* 0: physical, 1: logical */
 127                 delivery_status :  1,
 128                 polarity        :  1,
 129                 irr             :  1,
 130                 trigger         :  1,   /* 0: edge, 1: level */
 131                 mask            :  1,   /* 0: enabled, 1: disabled */
 132                 __reserved_2    : 15;
 133
 134         union {         struct { __u32
 135                                         __reserved_1    : 24,
 136                                         physical_dest   :  4,
 137                                         __reserved_2    :  4;
 138                         } physical;
 139
 140                         struct { __u32
 141                                         __reserved_1    : 24,
 142                                         logical_dest    :  8;
 143                         } logical;
 144         } dest;
 145
 146 } __attribute__ ((packed));
 147
 148 /*
 149  * MP-BIOS irq configuration table structures:
 150  */
 151
 152 /* I/O APIC entries */
 153 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
 154
 155 /* # of MP IRQ source entries */
 156 extern int mp_irq_entries;
 157
 158 /* MP IRQ source entries */
 159 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 160
 161 /* non-0 if default (table-less) MP configuration */
 162 extern int mpc_default_type;
 163
 164 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 165 {
 166         *IO_APIC_BASE(apic) = reg;
 167         return *(IO_APIC_BASE(apic)+4);
 168 }
 169
 170 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 171 {
 172         *IO_APIC_BASE(apic) = reg;
 173         *(IO_APIC_BASE(apic)+4) = value;
 174 }
 175
 176 /*
 177  * Re-write a value: to be used for read-modify-write
 178  * cycles where the read already set up the index register.
 179  */
 180 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 181 {
 182         *(IO_APIC_BASE(apic)+4) = value;
 183 }
 184
 185 /*
 186  * Synchronize the IO-APIC and the CPU by doing
 187  * a dummy read from the IO-APIC
 188  */
 189 static inline void io_apic_sync(unsigned int apic)
 190 {
 191         (void) *(IO_APIC_BASE(apic)+4);
 192 }
 193
 194 /* 1 if "noapic" boot option passed */
 195 extern int skip_ioapic_setup;
 196
 197 /*
 198  * If we use the IO-APIC for IRQ routing, disable automatic
 199  * assignment of PCI IRQ's.
 200  */
 201 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
 202
 203 #ifdef CONFIG_ACPI
 204 extern int io_apic_get_version (int ioapic);
 205 extern int io_apic_get_redir_entries (int ioapic);
 206 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
 207 extern int timer_uses_ioapic_pin_0;
 208 #endif
 209
 210 extern int sis_apic_bug; /* dummy */
 211
 212 #else  /* !CONFIG_X86_IO_APIC */
 213 #define io_apic_assign_pci_irqs 0
 214 #endif
 215
 216 extern int assign_irq_vector(int irq);
 217
 218 void enable_NMI_through_LVT0 (void * dummy);
 219
 220 extern spinlock_t i8259A_lock;
 221
 222 #endif