include/asm-x86_64/msr.h

   1 #ifndef X86_64_MSR_H
   2 #define X86_64_MSR_H 1
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Access to machine-specific registers (available on 586 and better only)
   7  * Note: the rd* operations modify the parameters directly (without using
   8  * pointer indirection), this allows gcc to optimize better
   9  */
  10
  11 #define rdmsr(msr,val1,val2) \
  12        __asm__ __volatile__("rdmsr" \
  13                             : "=a" (val1), "=d" (val2) \
  14                             : "c" (msr))
  15
  16
  17 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
  18        __asm__ __volatile__("rdmsr" \
  19                             : "=a" (a__), "=d" (b__) \
  20                             : "c" (msr)); \
  21        val = a__ | (b__<<32); \
  22 } while(0);
  23
  24 #define wrmsr(msr,val1,val2) \
  25      __asm__ __volatile__("wrmsr" \
  26                           : /* no outputs */ \
  27                           : "c" (msr), "a" (val1), "d" (val2))
  28
  29 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
  30
  31 /* wrmsr with exception handling */
  32 #define wrmsr_safe(msr,a,b) ({ int ret__;                                               \
  33         asm volatile("2: wrmsr ; xorl %0,%0\n"                                          \
  34                      "1:\n\t"                                                           \
  35                      ".section .fixup,\"ax\"\n\t"                                       \
  36                      "3:  movl %4,%0 ; jmp 1b\n\t"                                      \
  37                      ".previous\n\t"                                                    \
  38                      ".section __ex_table,\"a\"\n"                                      \
  39                      "   .align 8\n\t"                                                  \
  40                      "   .quad  2b,3b\n\t"                                              \
  41                      ".previous"                                                        \
  42                      : "=a" (ret__)                                                     \
  43                      : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
  44         ret__; })
  45
  46 #define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
  47
  48 #define rdtsc(low,high) \
  49      __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
  50
  51 #define rdtscl(low) \
  52      __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
  53
  54 #define rdtscll(val) do { \
  55      unsigned int __a,__d; \
  56      asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
  57      (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
  58 } while(0)
  59
  60 #define rdpmc(counter,low,high) \
  61      __asm__ __volatile__("rdpmc" \
  62                           : "=a" (low), "=d" (high) \
  63                           : "c" (counter))
  64
  65 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
  66
  67 #define rdpmc(counter,low,high) \
  68      __asm__ __volatile__("rdpmc" \
  69                           : "=a" (low), "=d" (high) \
  70                           : "c" (counter))
  71
  72 extern inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
  73                          unsigned int *ecx, unsigned int *edx)
  74 {
  75         __asm__("cpuid"
  76                 : "=a" (*eax),
  77                   "=b" (*ebx),
  78                   "=c" (*ecx),
  79                   "=d" (*edx)
  80                 : "0" (op));
  81 }
  82
  83 /* Some CPUID calls want 'count' to be placed in ecx */
  84 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
  85                 int *edx)
  86 {
  87         __asm__("cpuid"
  88                 : "=a" (*eax),
  89                   "=b" (*ebx),
  90                   "=c" (*ecx),
  91                   "=d" (*edx)
  92                 : "0" (op), "c" (count));
  93 }
  94
  95 /*
  96  * CPUID functions returning a single datum
  97  */
  98 extern inline unsigned int cpuid_eax(unsigned int op)
  99 {
 100         unsigned int eax;
 101
 102         __asm__("cpuid"
 103                 : "=a" (eax)
 104                 : "0" (op)
 105                 : "bx", "cx", "dx");
 106         return eax;
 107 }
 108 extern inline unsigned int cpuid_ebx(unsigned int op)
 109 {
 110         unsigned int eax, ebx;
 111
 112         __asm__("cpuid"
 113                 : "=a" (eax), "=b" (ebx)
 114                 : "0" (op)
 115                 : "cx", "dx" );
 116         return ebx;
 117 }
 118 extern inline unsigned int cpuid_ecx(unsigned int op)
 119 {
 120         unsigned int eax, ecx;
 121
 122         __asm__("cpuid"
 123                 : "=a" (eax), "=c" (ecx)
 124                 : "0" (op)
 125                 : "bx", "dx" );
 126         return ecx;
 127 }
 128 extern inline unsigned int cpuid_edx(unsigned int op)
 129 {
 130         unsigned int eax, edx;
 131
 132         __asm__("cpuid"
 133                 : "=a" (eax), "=d" (edx)
 134                 : "0" (op)
 135                 : "bx", "cx");
 136         return edx;
 137 }
 138
 139 #define MSR_IA32_UCODE_WRITE            0x79
 140 #define MSR_IA32_UCODE_REV              0x8b
 141
 142
 143 #endif
 144
 145 /* AMD/K8 specific MSRs */
 146 #define MSR_EFER 0xc0000080             /* extended feature register */
 147 #define MSR_STAR 0xc0000081             /* legacy mode SYSCALL target */
 148 #define MSR_LSTAR 0xc0000082            /* long mode SYSCALL target */
 149 #define MSR_CSTAR 0xc0000083            /* compatibility mode SYSCALL target */
 150 #define MSR_SYSCALL_MASK 0xc0000084     /* EFLAGS mask for syscall */
 151 #define MSR_FS_BASE 0xc0000100          /* 64bit GS base */
 152 #define MSR_GS_BASE 0xc0000101          /* 64bit FS base */
 153 #define MSR_KERNEL_GS_BASE  0xc0000102  /* SwapGS GS shadow (or USER_GS from kernel) */
 154 /* EFER bits: */
 155 #define _EFER_SCE 0  /* SYSCALL/SYSRET */
 156 #define _EFER_LME 8  /* Long mode enable */
 157 #define _EFER_LMA 10 /* Long mode active (read-only) */
 158 #define _EFER_NX 11  /* No execute enable */
 159
 160 #define EFER_SCE (1<<_EFER_SCE)
 161 #define EFER_LME (1<<_EFER_LME)
 162 #define EFER_LMA (1<<_EFER_LMA)
 163 #define EFER_NX (1<<_EFER_NX)
 164
 165 /* Intel MSRs. Some also available on other CPUs */
 166 #define MSR_IA32_PLATFORM_ID    0x17
 167
 168 #define MSR_IA32_PERFCTR0      0xc1
 169 #define MSR_IA32_PERFCTR1      0xc2
 170
 171 #define MSR_MTRRcap             0x0fe
 172 #define MSR_IA32_BBL_CR_CTL        0x119
 173
 174 #define MSR_IA32_SYSENTER_CS    0x174
 175 #define MSR_IA32_SYSENTER_ESP   0x175
 176 #define MSR_IA32_SYSENTER_EIP   0x176
 177
 178 #define MSR_IA32_MCG_CAP       0x179
 179 #define MSR_IA32_MCG_STATUS        0x17a
 180 #define MSR_IA32_MCG_CTL       0x17b
 181
 182 #define MSR_IA32_EVNTSEL0      0x186
 183 #define MSR_IA32_EVNTSEL1      0x187
 184
 185 #define MSR_IA32_DEBUGCTLMSR       0x1d9
 186 #define MSR_IA32_LASTBRANCHFROMIP  0x1db
 187 #define MSR_IA32_LASTBRANCHTOIP        0x1dc
 188 #define MSR_IA32_LASTINTFROMIP     0x1dd
 189 #define MSR_IA32_LASTINTTOIP       0x1de
 190
 191 #define MSR_MTRRfix64K_00000    0x250
 192 #define MSR_MTRRfix16K_80000    0x258
 193 #define MSR_MTRRfix16K_A0000    0x259
 194 #define MSR_MTRRfix4K_C0000     0x268
 195 #define MSR_MTRRfix4K_C8000     0x269
 196 #define MSR_MTRRfix4K_D0000     0x26a
 197 #define MSR_MTRRfix4K_D8000     0x26b
 198 #define MSR_MTRRfix4K_E0000     0x26c
 199 #define MSR_MTRRfix4K_E8000     0x26d
 200 #define MSR_MTRRfix4K_F0000     0x26e
 201 #define MSR_MTRRfix4K_F8000     0x26f
 202 #define MSR_MTRRdefType         0x2ff
 203
 204 #define MSR_IA32_MC0_CTL       0x400
 205 #define MSR_IA32_MC0_STATUS        0x401
 206 #define MSR_IA32_MC0_ADDR      0x402
 207 #define MSR_IA32_MC0_MISC      0x403
 208
 209 #define MSR_P6_PERFCTR0                 0xc1
 210 #define MSR_P6_PERFCTR1                 0xc2
 211 #define MSR_P6_EVNTSEL0                 0x186
 212 #define MSR_P6_EVNTSEL1                 0x187
 213
 214 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
 215 #define MSR_K7_EVNTSEL0            0xC0010000
 216 #define MSR_K7_PERFCTR0            0xC0010004
 217 #define MSR_K7_EVNTSEL1            0xC0010001
 218 #define MSR_K7_PERFCTR1            0xC0010005
 219 #define MSR_K7_EVNTSEL2            0xC0010002
 220 #define MSR_K7_PERFCTR2            0xC0010006
 221 #define MSR_K7_EVNTSEL3            0xC0010003
 222 #define MSR_K7_PERFCTR3            0xC0010007
 223 #define MSR_K8_TOP_MEM1            0xC001001A
 224 #define MSR_K8_TOP_MEM2            0xC001001D
 225 #define MSR_K8_SYSCFG              0xC0000010
 226
 227 /* K6 MSRs */
 228 #define MSR_K6_EFER                     0xC0000080
 229 #define MSR_K6_STAR                     0xC0000081
 230 #define MSR_K6_WHCR                     0xC0000082
 231 #define MSR_K6_UWCCR                    0xC0000085
 232 #define MSR_K6_PSOR                     0xC0000087
 233 #define MSR_K6_PFIR                     0xC0000088
 234
 235 /* Centaur-Hauls/IDT defined MSRs. */
 236 #define MSR_IDT_FCR1                    0x107
 237 #define MSR_IDT_FCR2                    0x108
 238 #define MSR_IDT_FCR3                    0x109
 239 #define MSR_IDT_FCR4                    0x10a
 240
 241 #define MSR_IDT_MCR0                    0x110
 242 #define MSR_IDT_MCR1                    0x111
 243 #define MSR_IDT_MCR2                    0x112
 244 #define MSR_IDT_MCR3                    0x113
 245 #define MSR_IDT_MCR4                    0x114
 246 #define MSR_IDT_MCR5                    0x115
 247 #define MSR_IDT_MCR6                    0x116
 248 #define MSR_IDT_MCR7                    0x117
 249 #define MSR_IDT_MCR_CTRL                0x120
 250
 251 /* VIA Cyrix defined MSRs*/
 252 #define MSR_VIA_FCR                     0x1107
 253 #define MSR_VIA_LONGHAUL                0x110a
 254 #define MSR_VIA_RNG                     0x110b
 255 #define MSR_VIA_BCR2                    0x1147
 256
 257 /* Intel defined MSRs. */
 258 #define MSR_IA32_P5_MC_ADDR             0
 259 #define MSR_IA32_P5_MC_TYPE             1
 260 #define MSR_IA32_PLATFORM_ID            0x17
 261 #define MSR_IA32_EBL_CR_POWERON         0x2a
 262
 263 #define MSR_IA32_APICBASE               0x1b
 264 #define MSR_IA32_APICBASE_BSP           (1<<8)
 265 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 266 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 267
 268 /* P4/Xeon+ specific */
 269 #define MSR_IA32_MCG_EAX                0x180
 270 #define MSR_IA32_MCG_EBX                0x181
 271 #define MSR_IA32_MCG_ECX                0x182
 272 #define MSR_IA32_MCG_EDX                0x183
 273 #define MSR_IA32_MCG_ESI                0x184
 274 #define MSR_IA32_MCG_EDI                0x185
 275 #define MSR_IA32_MCG_EBP                0x186
 276 #define MSR_IA32_MCG_ESP                0x187
 277 #define MSR_IA32_MCG_EFLAGS             0x188
 278 #define MSR_IA32_MCG_EIP                0x189
 279 #define MSR_IA32_MCG_RESERVED           0x18A
 280
 281 #define MSR_P6_EVNTSEL0                 0x186
 282 #define MSR_P6_EVNTSEL1                 0x187
 283
 284 #define MSR_IA32_PERF_STATUS            0x198
 285 #define MSR_IA32_PERF_CTL               0x199
 286
 287 #define MSR_IA32_THERM_CONTROL          0x19a
 288 #define MSR_IA32_THERM_INTERRUPT        0x19b
 289 #define MSR_IA32_THERM_STATUS           0x19c
 290 #define MSR_IA32_MISC_ENABLE            0x1a0
 291
 292 #define MSR_IA32_DEBUGCTLMSR            0x1d9
 293 #define MSR_IA32_LASTBRANCHFROMIP       0x1db
 294 #define MSR_IA32_LASTBRANCHTOIP         0x1dc
 295 #define MSR_IA32_LASTINTFROMIP          0x1dd
 296 #define MSR_IA32_LASTINTTOIP            0x1de
 297
 298 #define MSR_IA32_MC0_CTL                0x400
 299 #define MSR_IA32_MC0_STATUS             0x401
 300 #define MSR_IA32_MC0_ADDR               0x402
 301 #define MSR_IA32_MC0_MISC               0x403
 302
 303 /* Pentium IV performance counter MSRs */
 304 #define MSR_P4_BPU_PERFCTR0             0x300
 305 #define MSR_P4_BPU_PERFCTR1             0x301
 306 #define MSR_P4_BPU_PERFCTR2             0x302
 307 #define MSR_P4_BPU_PERFCTR3             0x303
 308 #define MSR_P4_MS_PERFCTR0              0x304
 309 #define MSR_P4_MS_PERFCTR1              0x305
 310 #define MSR_P4_MS_PERFCTR2              0x306
 311 #define MSR_P4_MS_PERFCTR3              0x307
 312 #define MSR_P4_FLAME_PERFCTR0           0x308
 313 #define MSR_P4_FLAME_PERFCTR1           0x309
 314 #define MSR_P4_FLAME_PERFCTR2           0x30a
 315 #define MSR_P4_FLAME_PERFCTR3           0x30b
 316 #define MSR_P4_IQ_PERFCTR0              0x30c
 317 #define MSR_P4_IQ_PERFCTR1              0x30d
 318 #define MSR_P4_IQ_PERFCTR2              0x30e
 319 #define MSR_P4_IQ_PERFCTR3              0x30f
 320 #define MSR_P4_IQ_PERFCTR4              0x310
 321 #define MSR_P4_IQ_PERFCTR5              0x311
 322 #define MSR_P4_BPU_CCCR0                0x360
 323 #define MSR_P4_BPU_CCCR1                0x361
 324 #define MSR_P4_BPU_CCCR2                0x362
 325 #define MSR_P4_BPU_CCCR3                0x363
 326 #define MSR_P4_MS_CCCR0                 0x364
 327 #define MSR_P4_MS_CCCR1                 0x365
 328 #define MSR_P4_MS_CCCR2                 0x366
 329 #define MSR_P4_MS_CCCR3                 0x367
 330 #define MSR_P4_FLAME_CCCR0              0x368
 331 #define MSR_P4_FLAME_CCCR1              0x369
 332 #define MSR_P4_FLAME_CCCR2              0x36a
 333 #define MSR_P4_FLAME_CCCR3              0x36b
 334 #define MSR_P4_IQ_CCCR0                 0x36c
 335 #define MSR_P4_IQ_CCCR1                 0x36d
 336 #define MSR_P4_IQ_CCCR2                 0x36e
 337 #define MSR_P4_IQ_CCCR3                 0x36f
 338 #define MSR_P4_IQ_CCCR4                 0x370
 339 #define MSR_P4_IQ_CCCR5                 0x371
 340 #define MSR_P4_ALF_ESCR0                0x3ca
 341 #define MSR_P4_ALF_ESCR1                0x3cb
 342 #define MSR_P4_BPU_ESCR0                0x3b2
 343 #define MSR_P4_BPU_ESCR1                0x3b3
 344 #define MSR_P4_BSU_ESCR0                0x3a0
 345 #define MSR_P4_BSU_ESCR1                0x3a1
 346 #define MSR_P4_CRU_ESCR0                0x3b8
 347 #define MSR_P4_CRU_ESCR1                0x3b9
 348 #define MSR_P4_CRU_ESCR2                0x3cc
 349 #define MSR_P4_CRU_ESCR3                0x3cd
 350 #define MSR_P4_CRU_ESCR4                0x3e0
 351 #define MSR_P4_CRU_ESCR5                0x3e1
 352 #define MSR_P4_DAC_ESCR0                0x3a8
 353 #define MSR_P4_DAC_ESCR1                0x3a9
 354 #define MSR_P4_FIRM_ESCR0               0x3a4
 355 #define MSR_P4_FIRM_ESCR1               0x3a5
 356 #define MSR_P4_FLAME_ESCR0              0x3a6
 357 #define MSR_P4_FLAME_ESCR1              0x3a7
 358 #define MSR_P4_FSB_ESCR0                0x3a2
 359 #define MSR_P4_FSB_ESCR1                0x3a3
 360 #define MSR_P4_IQ_ESCR0                 0x3ba
 361 #define MSR_P4_IQ_ESCR1                 0x3bb
 362 #define MSR_P4_IS_ESCR0                 0x3b4
 363 #define MSR_P4_IS_ESCR1                 0x3b5
 364 #define MSR_P4_ITLB_ESCR0               0x3b6
 365 #define MSR_P4_ITLB_ESCR1               0x3b7
 366 #define MSR_P4_IX_ESCR0                 0x3c8
 367 #define MSR_P4_IX_ESCR1                 0x3c9
 368 #define MSR_P4_MOB_ESCR0                0x3aa
 369 #define MSR_P4_MOB_ESCR1                0x3ab
 370 #define MSR_P4_MS_ESCR0                 0x3c0
 371 #define MSR_P4_MS_ESCR1                 0x3c1
 372 #define MSR_P4_PMH_ESCR0                0x3ac
 373 #define MSR_P4_PMH_ESCR1                0x3ad
 374 #define MSR_P4_RAT_ESCR0                0x3bc
 375 #define MSR_P4_RAT_ESCR1                0x3bd
 376 #define MSR_P4_SAAT_ESCR0               0x3ae
 377 #define MSR_P4_SAAT_ESCR1               0x3af
 378 #define MSR_P4_SSU_ESCR0                0x3be
 379 #define MSR_P4_SSU_ESCR1                0x3bf    /* guess: not defined in manual */
 380 #define MSR_P4_TBPU_ESCR0               0x3c2
 381 #define MSR_P4_TBPU_ESCR1               0x3c3
 382 #define MSR_P4_TC_ESCR0                 0x3c4
 383 #define MSR_P4_TC_ESCR1                 0x3c5
 384 #define MSR_P4_U2L_ESCR0                0x3b0
 385 #define MSR_P4_U2L_ESCR1                0x3b1
 386
 387 #endif