include/asm-x86_64/processor.h

   1 /*
   2  * include/asm-x86_64/processor.h
   3  *
   4  * Copyright (C) 1994 Linus Torvalds
   5  */
   6
   7 #ifndef __ASM_X86_64_PROCESSOR_H
   8 #define __ASM_X86_64_PROCESSOR_H
   9
  10 #include <asm/segment.h>
  11 #include <asm/page.h>
  12 #include <asm/types.h>
  13 #include <asm/sigcontext.h>
  14 #include <asm/cpufeature.h>
  15 #include <linux/threads.h>
  16 #include <asm/msr.h>
  17 #include <asm/current.h>
  18 #include <asm/system.h>
  19 #include <asm/mmsegment.h>
  20 #include <asm/percpu.h>
  21 #include <linux/personality.h>
  22 #include <linux/cpumask.h>
  23 #include <asm/processor-flags.h>
  24
  25 #define TF_MASK         0x00000100
  26 #define IF_MASK         0x00000200
  27 #define IOPL_MASK       0x00003000
  28 #define NT_MASK         0x00004000
  29 #define VM_MASK         0x00020000
  30 #define AC_MASK         0x00040000
  31 #define VIF_MASK        0x00080000      /* virtual interrupt flag */
  32 #define VIP_MASK        0x00100000      /* virtual interrupt pending */
  33 #define ID_MASK         0x00200000
  34
  35 #define desc_empty(desc) \
  36                (!((desc)->a | (desc)->b))
  37
  38 #define desc_equal(desc1, desc2) \
  39                (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
  40
  41 /*
  42  * Default implementation of macro that returns current
  43  * instruction pointer ("program counter").
  44  */
  45 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
  46
  47 /*
  48  *  CPU type and hardware bug flags. Kept separately for each CPU.
  49  */
  50
  51 struct cpuinfo_x86 {
  52         __u8    x86;            /* CPU family */
  53         __u8    x86_vendor;     /* CPU vendor */
  54         __u8    x86_model;
  55         __u8    x86_mask;
  56         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  57         __u32   x86_capability[NCAPINTS];
  58         char    x86_vendor_id[16];
  59         char    x86_model_id[64];
  60         int     x86_cache_size;  /* in KB */
  61         int     x86_clflush_size;
  62         int     x86_cache_alignment;
  63         int     x86_tlbsize;    /* number of 4K pages in DTLB/ITLB combined(in pages)*/
  64         __u8    x86_virt_bits, x86_phys_bits;
  65         __u8    x86_max_cores;  /* cpuid returned max cores value */
  66         __u32   x86_power;
  67         __u32   extended_cpuid_level;   /* Max extended CPUID function supported */
  68         unsigned long loops_per_jiffy;
  69 #ifdef CONFIG_SMP
  70         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  71 #endif
  72         __u8    apicid;
  73 #ifdef CONFIG_SMP
  74         __u8    booted_cores;   /* number of cores as seen by OS */
  75         __u8    phys_proc_id;   /* Physical Processor id. */
  76         __u8    cpu_core_id;    /* Core id. */
  77 #endif
  78 } ____cacheline_aligned;
  79
  80 #define X86_VENDOR_INTEL 0
  81 #define X86_VENDOR_CYRIX 1
  82 #define X86_VENDOR_AMD 2
  83 #define X86_VENDOR_UMC 3
  84 #define X86_VENDOR_NEXGEN 4
  85 #define X86_VENDOR_CENTAUR 5
  86 #define X86_VENDOR_RISE 6
  87 #define X86_VENDOR_TRANSMETA 7
  88 #define X86_VENDOR_NUM 8
  89 #define X86_VENDOR_UNKNOWN 0xff
  90
  91 #ifdef CONFIG_SMP
  92 extern struct cpuinfo_x86 cpu_data[];
  93 #define current_cpu_data cpu_data[smp_processor_id()]
  94 #else
  95 #define cpu_data (&boot_cpu_data)
  96 #define current_cpu_data boot_cpu_data
  97 #endif
  98
  99 extern char ignore_irq13;
 100
 101 extern void identify_cpu(struct cpuinfo_x86 *);
 102 extern void print_cpu_info(struct cpuinfo_x86 *);
 103 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 104 extern unsigned short num_cache_leaves;
 105
 106 /*
 107  * Intel CPU features in CR4
 108  */
 109 #define X86_CR4_VME             0x0001  /* enable vm86 extensions */
 110 #define X86_CR4_PVI             0x0002  /* virtual interrupts flag enable */
 111 #define X86_CR4_TSD             0x0004  /* disable time stamp at ipl 3 */
 112 #define X86_CR4_DE              0x0008  /* enable debugging extensions */
 113 #define X86_CR4_PSE             0x0010  /* enable page size extensions */
 114 #define X86_CR4_PAE             0x0020  /* enable physical address extensions */
 115 #define X86_CR4_MCE             0x0040  /* Machine check enable */
 116 #define X86_CR4_PGE             0x0080  /* enable global pages */
 117 #define X86_CR4_PCE             0x0100  /* enable performance counters at ipl 3 */
 118 #define X86_CR4_OSFXSR          0x0200  /* enable fast FPU save and restore */
 119 #define X86_CR4_OSXMMEXCPT      0x0400  /* enable unmasked SSE exceptions */
 120
 121 /*
 122  * Save the cr4 feature set we're using (ie
 123  * Pentium 4MB enable and PPro Global page
 124  * enable), so that any CPU's that boot up
 125  * after us can get the correct flags.
 126  */
 127 extern unsigned long mmu_cr4_features;
 128
 129 static inline void set_in_cr4 (unsigned long mask)
 130 {
 131         mmu_cr4_features |= mask;
 132         __asm__("movq %%cr4,%%rax\n\t"
 133                 "orq %0,%%rax\n\t"
 134                 "movq %%rax,%%cr4\n"
 135                 : : "irg" (mask)
 136                 :"ax");
 137 }
 138
 139 static inline void clear_in_cr4 (unsigned long mask)
 140 {
 141         mmu_cr4_features &= ~mask;
 142         __asm__("movq %%cr4,%%rax\n\t"
 143                 "andq %0,%%rax\n\t"
 144                 "movq %%rax,%%cr4\n"
 145                 : : "irg" (~mask)
 146                 :"ax");
 147 }
 148
 149
 150 /*
 151  * User space process size. 47bits minus one guard page.
 152  */
 153 #define TASK_SIZE64     (0x800000000000UL - 4096)
 154
 155 /* This decides where the kernel will search for a free chunk of vm
 156  * space during mmap's.
 157  */
 158 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
 159
 160 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
 161 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
 162
 163 #define TASK_UNMAPPED_BASE      PAGE_ALIGN(TASK_SIZE/3)
 164
 165 /*
 166  * Size of io_bitmap.
 167  */
 168 #define IO_BITMAP_BITS  65536
 169 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 170 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 171 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 172 #define INVALID_IO_BITMAP_OFFSET 0x8000
 173
 174 struct i387_fxsave_struct {
 175         u16     cwd;
 176         u16     swd;
 177         u16     twd;
 178         u16     fop;
 179         u64     rip;
 180         u64     rdp;
 181         u32     mxcsr;
 182         u32     mxcsr_mask;
 183         u32     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 184         u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 128 bytes */
 185         u32     padding[24];
 186 } __attribute__ ((aligned (16)));
 187
 188 union i387_union {
 189         struct i387_fxsave_struct       fxsave;
 190 };
 191
 192 struct tss_struct {
 193         u32 reserved1;
 194         u64 rsp0;
 195         u64 rsp1;
 196         u64 rsp2;
 197         u64 reserved2;
 198         u64 ist[7];
 199         u32 reserved3;
 200         u32 reserved4;
 201         u16 reserved5;
 202         u16 io_bitmap_base;
 203         /*
 204          * The extra 1 is there because the CPU will access an
 205          * additional byte beyond the end of the IO permission
 206          * bitmap. The extra byte must be all 1 bits, and must
 207          * be within the limit. Thus we have:
 208          *
 209          * 128 bytes, the bitmap itself, for ports 0..0x3ff
 210          * 8 bytes, for an extra "long" of ~0UL
 211          */
 212         unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
 213 } __attribute__((packed)) ____cacheline_aligned;
 214
 215
 216 extern struct cpuinfo_x86 boot_cpu_data;
 217 DECLARE_PER_CPU(struct tss_struct,init_tss);
 218 /* Save the original ist values for checking stack pointers during debugging */
 219 struct orig_ist {
 220         unsigned long ist[7];
 221 };
 222 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 223
 224 #ifdef CONFIG_X86_VSMP
 225 #define ARCH_MIN_TASKALIGN      (1 << INTERNODE_CACHE_SHIFT)
 226 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
 227 #else
 228 #define ARCH_MIN_TASKALIGN      16
 229 #define ARCH_MIN_MMSTRUCT_ALIGN 0
 230 #endif
 231
 232 struct thread_struct {
 233         unsigned long   rsp0;
 234         unsigned long   rsp;
 235         unsigned long   userrsp;        /* Copy from PDA */
 236         unsigned long   fs;
 237         unsigned long   gs;
 238         unsigned short  es, ds, fsindex, gsindex;
 239 /* Hardware debugging registers */
 240         unsigned long   debugreg0;
 241         unsigned long   debugreg1;
 242         unsigned long   debugreg2;
 243         unsigned long   debugreg3;
 244         unsigned long   debugreg6;
 245         unsigned long   debugreg7;
 246 /* fault info */
 247         unsigned long   cr2, trap_no, error_code;
 248 /* floating point info */
 249         union i387_union        i387  __attribute__((aligned(16)));
 250 /* IO permissions. the bitmap could be moved into the GDT, that would make
 251    switch faster for a limited number of ioperm using tasks. -AK */
 252         int             ioperm;
 253         unsigned long   *io_bitmap_ptr;
 254         unsigned io_bitmap_max;
 255 /* cached TLS descriptors. */
 256         u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
 257 } __attribute__((aligned(16)));
 258
 259 #define INIT_THREAD  { \
 260         .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 261 }
 262
 263 #define INIT_TSS  { \
 264         .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 265 }
 266
 267 #define INIT_MMAP \
 268 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
 269
 270 #define start_thread(regs,new_rip,new_rsp) do { \
 271         asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0));      \
 272         load_gs_index(0);                                                       \
 273         (regs)->rip = (new_rip);                                                 \
 274         (regs)->rsp = (new_rsp);                                                 \
 275         write_pda(oldrsp, (new_rsp));                                            \
 276         (regs)->cs = __USER_CS;                                                  \
 277         (regs)->ss = __USER_DS;                                                  \
 278         (regs)->eflags = 0x200;                                                  \
 279         set_fs(USER_DS);                                                         \
 280 } while(0)
 281
 282 #define get_debugreg(var, register)                             \
 283                 __asm__("movq %%db" #register ", %0"            \
 284                         :"=r" (var))
 285 #define set_debugreg(value, register)                   \
 286                 __asm__("movq %0,%%db" #register                \
 287                         : /* no output */                       \
 288                         :"r" (value))
 289
 290 struct task_struct;
 291 struct mm_struct;
 292
 293 /* Free all resources held by a thread. */
 294 extern void release_thread(struct task_struct *);
 295
 296 /* Prepare to copy thread state - unlazy all lazy status */
 297 extern void prepare_to_copy(struct task_struct *tsk);
 298
 299 /*
 300  * create a kernel thread without removing it from tasklists
 301  */
 302 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 303
 304 /*
 305  * Return saved PC of a blocked thread.
 306  * What is this good for? it will be always the scheduler or ret_from_fork.
 307  */
 308 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
 309
 310 extern unsigned long get_wchan(struct task_struct *p);
 311 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.rsp0 - 1)
 312 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->rip)
 313 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
 314
 315
 316 struct microcode_header {
 317         unsigned int hdrver;
 318         unsigned int rev;
 319         unsigned int date;
 320         unsigned int sig;
 321         unsigned int cksum;
 322         unsigned int ldrver;
 323         unsigned int pf;
 324         unsigned int datasize;
 325         unsigned int totalsize;
 326         unsigned int reserved[3];
 327 };
 328
 329 struct microcode {
 330         struct microcode_header hdr;
 331         unsigned int bits[0];
 332 };
 333
 334 typedef struct microcode microcode_t;
 335 typedef struct microcode_header microcode_header_t;
 336
 337 /* microcode format is extended from prescott processors */
 338 struct extended_signature {
 339         unsigned int sig;
 340         unsigned int pf;
 341         unsigned int cksum;
 342 };
 343
 344 struct extended_sigtable {
 345         unsigned int count;
 346         unsigned int cksum;
 347         unsigned int reserved[3];
 348         struct extended_signature sigs[0];
 349 };
 350
 351
 352 #define ASM_NOP1 K8_NOP1
 353 #define ASM_NOP2 K8_NOP2
 354 #define ASM_NOP3 K8_NOP3
 355 #define ASM_NOP4 K8_NOP4
 356 #define ASM_NOP5 K8_NOP5
 357 #define ASM_NOP6 K8_NOP6
 358 #define ASM_NOP7 K8_NOP7
 359 #define ASM_NOP8 K8_NOP8
 360
 361 /* Opteron nops */
 362 #define K8_NOP1 ".byte 0x90\n"
 363 #define K8_NOP2 ".byte 0x66,0x90\n"
 364 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 365 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 366 #define K8_NOP5 K8_NOP3 K8_NOP2
 367 #define K8_NOP6 K8_NOP3 K8_NOP3
 368 #define K8_NOP7 K8_NOP4 K8_NOP3
 369 #define K8_NOP8 K8_NOP4 K8_NOP4
 370
 371 #define ASM_NOP_MAX 8
 372
 373 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 374 static inline void rep_nop(void)
 375 {
 376         __asm__ __volatile__("rep;nop": : :"memory");
 377 }
 378
 379 /* Stop speculative execution */
 380 static inline void sync_core(void)
 381 {
 382         int tmp;
 383         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 384 }
 385
 386 #define cpu_has_fpu 1
 387
 388 #define ARCH_HAS_PREFETCH
 389 static inline void prefetch(void *x)
 390 {
 391         asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
 392 }
 393
 394 #define ARCH_HAS_PREFETCHW 1
 395 static inline void prefetchw(void *x)
 396 {
 397         alternative_input("prefetcht0 (%1)",
 398                           "prefetchw (%1)",
 399                           X86_FEATURE_3DNOW,
 400                           "r" (x));
 401 }
 402
 403 #define ARCH_HAS_SPINLOCK_PREFETCH 1
 404
 405 #define spin_lock_prefetch(x)  prefetchw(x)
 406
 407 #define cpu_relax()   rep_nop()
 408
 409 /*
 410  *      NSC/Cyrix CPU configuration register indexes
 411  */
 412 #define CX86_CCR0 0xc0
 413 #define CX86_CCR1 0xc1
 414 #define CX86_CCR2 0xc2
 415 #define CX86_CCR3 0xc3
 416 #define CX86_CCR4 0xe8
 417 #define CX86_CCR5 0xe9
 418 #define CX86_CCR6 0xea
 419 #define CX86_CCR7 0xeb
 420 #define CX86_DIR0 0xfe
 421 #define CX86_DIR1 0xff
 422 #define CX86_ARR_BASE 0xc4
 423 #define CX86_RCR_BASE 0xdc
 424
 425 /*
 426  *      NSC/Cyrix CPU indexed register access macros
 427  */
 428
 429 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
 430
 431 #define setCx86(reg, data) do { \
 432         outb((reg), 0x22); \
 433         outb((data), 0x23); \
 434 } while (0)
 435
 436 static inline void serialize_cpu(void)
 437 {
 438         __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
 439 }
 440
 441 static inline void __monitor(const void *eax, unsigned long ecx,
 442                 unsigned long edx)
 443 {
 444         /* "monitor %eax,%ecx,%edx;" */
 445         asm volatile(
 446                 ".byte 0x0f,0x01,0xc8;"
 447                 : :"a" (eax), "c" (ecx), "d"(edx));
 448 }
 449
 450 static inline void __mwait(unsigned long eax, unsigned long ecx)
 451 {
 452         /* "mwait %eax,%ecx;" */
 453         asm volatile(
 454                 ".byte 0x0f,0x01,0xc9;"
 455                 : :"a" (eax), "c" (ecx));
 456 }
 457
 458 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 459 {
 460         /* "mwait %eax,%ecx;" */
 461         asm volatile(
 462                 "sti; .byte 0x0f,0x01,0xc9;"
 463                 : :"a" (eax), "c" (ecx));
 464 }
 465
 466 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 467
 468 #define stack_current() \
 469 ({                                                              \
 470         struct thread_info *ti;                                 \
 471         asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK));  \
 472         ti->task;                                       \
 473 })
 474
 475 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 476
 477 extern unsigned long boot_option_idle_override;
 478 /* Boot loader type from the setup header */
 479 extern int bootloader_type;
 480
 481 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 482
 483 #endif /* __ASM_X86_64_PROCESSOR_H */