include/dt-bindings/clock/marvell,mmp2.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __DTS_MARVELL_MMP2_CLOCK_H
   3 #define __DTS_MARVELL_MMP2_CLOCK_H
   4
   5 /* fixed clocks and plls */
   6 #define MMP2_CLK_CLK32                  1
   7 #define MMP2_CLK_VCTCXO                 2
   8 #define MMP2_CLK_PLL1                   3
   9 #define MMP2_CLK_PLL1_2                 8
  10 #define MMP2_CLK_PLL1_4                 9
  11 #define MMP2_CLK_PLL1_8                 10
  12 #define MMP2_CLK_PLL1_16                11
  13 #define MMP2_CLK_PLL1_3                 12
  14 #define MMP2_CLK_PLL1_6                 13
  15 #define MMP2_CLK_PLL1_12                14
  16 #define MMP2_CLK_PLL1_20                15
  17 #define MMP2_CLK_PLL2                   16
  18 #define MMP2_CLK_PLL2_2                 17
  19 #define MMP2_CLK_PLL2_4                 18
  20 #define MMP2_CLK_PLL2_8                 19
  21 #define MMP2_CLK_PLL2_16                20
  22 #define MMP2_CLK_PLL2_3                 21
  23 #define MMP2_CLK_PLL2_6                 22
  24 #define MMP2_CLK_PLL2_12                23
  25 #define MMP2_CLK_VCTCXO_2               24
  26 #define MMP2_CLK_VCTCXO_4               25
  27 #define MMP2_CLK_UART_PLL               26
  28 #define MMP2_CLK_USB_PLL                27
  29
  30 /* apb periphrals */
  31 #define MMP2_CLK_TWSI0                  60
  32 #define MMP2_CLK_TWSI1                  61
  33 #define MMP2_CLK_TWSI2                  62
  34 #define MMP2_CLK_TWSI3                  63
  35 #define MMP2_CLK_TWSI4                  64
  36 #define MMP2_CLK_TWSI5                  65
  37 #define MMP2_CLK_GPIO                   66
  38 #define MMP2_CLK_KPC                    67
  39 #define MMP2_CLK_RTC                    68
  40 #define MMP2_CLK_PWM0                   69
  41 #define MMP2_CLK_PWM1                   70
  42 #define MMP2_CLK_PWM2                   71
  43 #define MMP2_CLK_PWM3                   72
  44 #define MMP2_CLK_UART0                  73
  45 #define MMP2_CLK_UART1                  74
  46 #define MMP2_CLK_UART2                  75
  47 #define MMP2_CLK_UART3                  76
  48 #define MMP2_CLK_SSP0                   77
  49 #define MMP2_CLK_SSP1                   78
  50 #define MMP2_CLK_SSP2                   79
  51 #define MMP2_CLK_SSP3                   80
  52 #define MMP2_CLK_TIMER                  81
  53
  54 /* axi periphrals */
  55 #define MMP2_CLK_SDH0                   101
  56 #define MMP2_CLK_SDH1                   102
  57 #define MMP2_CLK_SDH2                   103
  58 #define MMP2_CLK_SDH3                   104
  59 #define MMP2_CLK_USB                    105
  60 #define MMP2_CLK_DISP0                  106
  61 #define MMP2_CLK_DISP0_MUX              107
  62 #define MMP2_CLK_DISP0_SPHY             108
  63 #define MMP2_CLK_DISP1                  109
  64 #define MMP2_CLK_DISP1_MUX              110
  65 #define MMP2_CLK_CCIC_ARBITER           111
  66 #define MMP2_CLK_CCIC0                  112
  67 #define MMP2_CLK_CCIC0_MIX              113
  68 #define MMP2_CLK_CCIC0_PHY              114
  69 #define MMP2_CLK_CCIC0_SPHY             115
  70 #define MMP2_CLK_CCIC1                  116
  71 #define MMP2_CLK_CCIC1_MIX              117
  72 #define MMP2_CLK_CCIC1_PHY              118
  73 #define MMP2_CLK_CCIC1_SPHY             119
  74
  75 #define MMP2_NR_CLKS                    200
  76 #endif