]>
git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - include/dt-bindings/clock/rk3188-cru-common.h
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
19 /* core clocks from */
28 /* sclk gates (special clocks) */
36 #define SCLK_SARADC 71
46 #define SCLK_OTGPHY0 81
47 #define SCLK_OTGPHY1 82
49 #define SCLK_TIMER0 84
50 #define SCLK_TIMER1 85
51 #define SCLK_TIMER2 86
52 #define SCLK_TIMER3 87
53 #define SCLK_TIMER4 88
54 #define SCLK_TIMER5 89
55 #define SCLK_TIMER6 90
59 #define DCLK_LCDC0 190
60 #define DCLK_LCDC1 191
66 #define ACLK_LCDC0 195
67 #define ACLK_LCDC1 196
78 #define PCLK_TIMER0 322
79 #define PCLK_TIMER1 323
80 #define PCLK_TIMER2 324
81 #define PCLK_TIMER3 325
82 #define PCLK_PWM01 326
83 #define PCLK_PWM23 327
86 #define PCLK_SARADC 330
88 #define PCLK_UART0 332
89 #define PCLK_UART1 333
90 #define PCLK_UART2 334
91 #define PCLK_UART3 335
97 #define PCLK_GPIO0 341
98 #define PCLK_GPIO1 342
99 #define PCLK_GPIO2 343
100 #define PCLK_GPIO3 344
101 #define PCLK_GPIO4 345
102 #define PCLK_GPIO6 346
103 #define PCLK_EFUSE 347
104 #define PCLK_TZPC 348
105 #define PCLK_TSADC 349
108 #define HCLK_SDMMC 448
109 #define HCLK_SDIO 449
110 #define HCLK_EMMC 450
111 #define HCLK_OTG0 451
112 #define HCLK_EMAC 452
113 #define HCLK_SPDIF 453
114 #define HCLK_I2S0 454
115 #define HCLK_I2S1 455
116 #define HCLK_I2S2 456
117 #define HCLK_OTG1 457
118 #define HCLK_HSIC 458
119 #define HCLK_HSADC 459
120 #define HCLK_PIDF 460
121 #define HCLK_LCDC0 461
122 #define HCLK_LCDC1 462
124 #define HCLK_CIF0 464
127 #define HCLK_NANDC0 467
129 #define CLK_NR_CLKS (HCLK_NANDC0 + 1)
131 /* soft-reset indices */
135 #define SRST_MCORE_DBG 7
136 #define SRST_CORE0_DBG 8
137 #define SRST_CORE1_DBG 9
138 #define SRST_CORE0_WDT 12
139 #define SRST_CORE1_WDT 13
140 #define SRST_STRC_SYS 14
143 #define SRST_CPU_AHB 17
144 #define SRST_AHB2APB 19
146 #define SRST_INTMEM 21
148 #define SRST_SPDIF 26
149 #define SRST_TIMER0 27
150 #define SRST_TIMER1 28
151 #define SRST_EFUSE 30
153 #define SRST_GPIO0 32
154 #define SRST_GPIO1 33
155 #define SRST_GPIO2 34
156 #define SRST_GPIO3 35
158 #define SRST_UART0 39
159 #define SRST_UART1 40
160 #define SRST_UART2 41
161 #define SRST_UART3 42
170 #define SRST_DAP_PO 50
172 #define SRST_DAP_SYS 52
173 #define SRST_TPIU_ATB 53
174 #define SRST_PMU_APB 54
177 #define SRST_PERI_AXI 57
178 #define SRST_PERI_AHB 58
179 #define SRST_PERI_APB 59
180 #define SRST_PERI_NIU 60
181 #define SRST_CPU_PERI 61
182 #define SRST_EMEM_PERI 62
183 #define SRST_USB_PERI 63
188 #define SRST_NANC0 68
189 #define SRST_USBOTG0 69
190 #define SRST_USBPHY0 70
191 #define SRST_OTGC0 71
192 #define SRST_USBOTG1 72
193 #define SRST_USBPHY1 73
194 #define SRST_OTGC1 74
195 #define SRST_HSADC 76
196 #define SRST_PIDFILTER 77
197 #define SRST_DDR_MSCH 79
200 #define SRST_SDMMC 81
206 #define SRST_SARADC 87
207 #define SRST_DDRPHY 88
208 #define SRST_DDRPHY_APB 89
209 #define SRST_DDRCTL 90
210 #define SRST_DDRCTL_APB 91
211 #define SRST_DDRPUB 93
213 #define SRST_VIO0_AXI 98
214 #define SRST_VIO0_AHB 99
215 #define SRST_LCDC0_AXI 100
216 #define SRST_LCDC0_AHB 101
217 #define SRST_LCDC0_DCLK 102
218 #define SRST_LCDC1_AXI 103
219 #define SRST_LCDC1_AHB 104
220 #define SRST_LCDC1_DCLK 105
221 #define SRST_IPP_AXI 106
222 #define SRST_IPP_AHB 107
223 #define SRST_RGA_AXI 108
224 #define SRST_RGA_AHB 109
225 #define SRST_CIF0 110
227 #define SRST_VCODEC_AXI 112
228 #define SRST_VCODEC_AHB 113
229 #define SRST_VIO1_AXI 114
230 #define SRST_VCODEC_CPU 115
231 #define SRST_VCODEC_NIU 116
233 #define SRST_GPU_NIU 122
234 #define SRST_TFUN_ATB 125
235 #define SRST_TFUN_APB 126
236 #define SRST_CTI4_APB 127
238 #define SRST_TPIU_APB 128
239 #define SRST_TRACE 129
240 #define SRST_CORE_DBG 130
241 #define SRST_DBG_APB 131
242 #define SRST_CTI0 132
243 #define SRST_CTI0_APB 133
244 #define SRST_CTI1 134
245 #define SRST_CTI1_APB 135
246 #define SRST_PTM_CORE0 136
247 #define SRST_PTM_CORE1 137
248 #define SRST_PTM0 138
249 #define SRST_PTM0_ATB 139
250 #define SRST_PTM1 140
251 #define SRST_PTM1_ATB 141