include/dt-bindings/clock/rk3188-cru-common.h

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
  17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
  18
  19 /* core clocks from */
  20 #define PLL_APLL                1
  21 #define PLL_DPLL                2
  22 #define PLL_CPLL                3
  23 #define PLL_GPLL                4
  24 #define CORE_PERI               5
  25 #define CORE_L2C                6
  26 #define ARMCLK                  7
  27
  28 /* sclk gates (special clocks) */
  29 #define SCLK_UART0              64
  30 #define SCLK_UART1              65
  31 #define SCLK_UART2              66
  32 #define SCLK_UART3              67
  33 #define SCLK_MAC                68
  34 #define SCLK_SPI0               69
  35 #define SCLK_SPI1               70
  36 #define SCLK_SARADC             71
  37 #define SCLK_SDMMC              72
  38 #define SCLK_SDIO               73
  39 #define SCLK_EMMC               74
  40 #define SCLK_I2S0               75
  41 #define SCLK_I2S1               76
  42 #define SCLK_I2S2               77
  43 #define SCLK_SPDIF              78
  44 #define SCLK_CIF0               79
  45 #define SCLK_CIF1               80
  46 #define SCLK_OTGPHY0            81
  47 #define SCLK_OTGPHY1            82
  48 #define SCLK_HSADC              83
  49 #define SCLK_TIMER0             84
  50 #define SCLK_TIMER1             85
  51 #define SCLK_TIMER2             86
  52 #define SCLK_TIMER3             87
  53 #define SCLK_TIMER4             88
  54 #define SCLK_TIMER5             89
  55 #define SCLK_TIMER6             90
  56 #define SCLK_JTAG               91
  57 #define SCLK_SMC                92
  58 #define SCLK_TSADC              93
  59
  60 #define DCLK_LCDC0              190
  61 #define DCLK_LCDC1              191
  62
  63 /* aclk gates */
  64 #define ACLK_DMA1               192
  65 #define ACLK_DMA2               193
  66 #define ACLK_GPS                194
  67 #define ACLK_LCDC0              195
  68 #define ACLK_LCDC1              196
  69 #define ACLK_GPU                197
  70 #define ACLK_SMC                198
  71 #define ACLK_CIF1               199
  72 #define ACLK_IPP                200
  73 #define ACLK_RGA                201
  74 #define ACLK_CIF0               202
  75 #define ACLK_CPU                203
  76 #define ACLK_PERI               204
  77 #define ACLK_VEPU               205
  78 #define ACLK_VDPU               206
  79
  80 /* pclk gates */
  81 #define PCLK_GRF                320
  82 #define PCLK_PMU                321
  83 #define PCLK_TIMER0             322
  84 #define PCLK_TIMER1             323
  85 #define PCLK_TIMER2             324
  86 #define PCLK_TIMER3             325
  87 #define PCLK_PWM01              326
  88 #define PCLK_PWM23              327
  89 #define PCLK_SPI0               328
  90 #define PCLK_SPI1               329
  91 #define PCLK_SARADC             330
  92 #define PCLK_WDT                331
  93 #define PCLK_UART0              332
  94 #define PCLK_UART1              333
  95 #define PCLK_UART2              334
  96 #define PCLK_UART3              335
  97 #define PCLK_I2C0               336
  98 #define PCLK_I2C1               337
  99 #define PCLK_I2C2               338
 100 #define PCLK_I2C3               339
 101 #define PCLK_I2C4               340
 102 #define PCLK_GPIO0              341
 103 #define PCLK_GPIO1              342
 104 #define PCLK_GPIO2              343
 105 #define PCLK_GPIO3              344
 106 #define PCLK_GPIO4              345
 107 #define PCLK_GPIO6              346
 108 #define PCLK_EFUSE              347
 109 #define PCLK_TZPC               348
 110 #define PCLK_TSADC              349
 111 #define PCLK_CPU                350
 112 #define PCLK_PERI               351
 113 #define PCLK_DDRUPCTL           352
 114 #define PCLK_PUBL               353
 115
 116 /* hclk gates */
 117 #define HCLK_SDMMC              448
 118 #define HCLK_SDIO               449
 119 #define HCLK_EMMC               450
 120 #define HCLK_OTG0               451
 121 #define HCLK_EMAC               452
 122 #define HCLK_SPDIF              453
 123 #define HCLK_I2S0               454
 124 #define HCLK_I2S1               455
 125 #define HCLK_I2S2               456
 126 #define HCLK_OTG1               457
 127 #define HCLK_HSIC               458
 128 #define HCLK_HSADC              459
 129 #define HCLK_PIDF               460
 130 #define HCLK_LCDC0              461
 131 #define HCLK_LCDC1              462
 132 #define HCLK_ROM                463
 133 #define HCLK_CIF0               464
 134 #define HCLK_IPP                465
 135 #define HCLK_RGA                466
 136 #define HCLK_NANDC0             467
 137 #define HCLK_CPU                468
 138 #define HCLK_PERI               469
 139 #define HCLK_CIF1               470
 140 #define HCLK_VEPU               471
 141 #define HCLK_VDPU               472
 142
 143 #define CLK_NR_CLKS             (HCLK_VDPU + 1)
 144
 145 /* soft-reset indices */
 146 #define SRST_MCORE              2
 147 #define SRST_CORE0              3
 148 #define SRST_CORE1              4
 149 #define SRST_MCORE_DBG          7
 150 #define SRST_CORE0_DBG          8
 151 #define SRST_CORE1_DBG          9
 152 #define SRST_CORE0_WDT          12
 153 #define SRST_CORE1_WDT          13
 154 #define SRST_STRC_SYS           14
 155 #define SRST_L2C                15
 156
 157 #define SRST_CPU_AHB            17
 158 #define SRST_AHB2APB            19
 159 #define SRST_DMA1               20
 160 #define SRST_INTMEM             21
 161 #define SRST_ROM                22
 162 #define SRST_SPDIF              26
 163 #define SRST_TIMER0             27
 164 #define SRST_TIMER1             28
 165 #define SRST_EFUSE              30
 166
 167 #define SRST_GPIO0              32
 168 #define SRST_GPIO1              33
 169 #define SRST_GPIO2              34
 170 #define SRST_GPIO3              35
 171
 172 #define SRST_UART0              39
 173 #define SRST_UART1              40
 174 #define SRST_UART2              41
 175 #define SRST_UART3              42
 176 #define SRST_I2C0               43
 177 #define SRST_I2C1               44
 178 #define SRST_I2C2               45
 179 #define SRST_I2C3               46
 180 #define SRST_I2C4               47
 181
 182 #define SRST_PWM0               48
 183 #define SRST_PWM1               49
 184 #define SRST_DAP_PO             50
 185 #define SRST_DAP                51
 186 #define SRST_DAP_SYS            52
 187 #define SRST_TPIU_ATB           53
 188 #define SRST_PMU_APB            54
 189 #define SRST_GRF                55
 190 #define SRST_PMU                56
 191 #define SRST_PERI_AXI           57
 192 #define SRST_PERI_AHB           58
 193 #define SRST_PERI_APB           59
 194 #define SRST_PERI_NIU           60
 195 #define SRST_CPU_PERI           61
 196 #define SRST_EMEM_PERI          62
 197 #define SRST_USB_PERI           63
 198
 199 #define SRST_DMA2               64
 200 #define SRST_SMC                65
 201 #define SRST_MAC                66
 202 #define SRST_NANC0              68
 203 #define SRST_USBOTG0            69
 204 #define SRST_USBPHY0            70
 205 #define SRST_OTGC0              71
 206 #define SRST_USBOTG1            72
 207 #define SRST_USBPHY1            73
 208 #define SRST_OTGC1              74
 209 #define SRST_HSADC              76
 210 #define SRST_PIDFILTER          77
 211 #define SRST_DDR_MSCH           79
 212
 213 #define SRST_TZPC               80
 214 #define SRST_SDMMC              81
 215 #define SRST_SDIO               82
 216 #define SRST_EMMC               83
 217 #define SRST_SPI0               84
 218 #define SRST_SPI1               85
 219 #define SRST_WDT                86
 220 #define SRST_SARADC             87
 221 #define SRST_DDRPHY             88
 222 #define SRST_DDRPHY_APB         89
 223 #define SRST_DDRCTL             90
 224 #define SRST_DDRCTL_APB         91
 225 #define SRST_DDRPUB             93
 226
 227 #define SRST_VIO0_AXI           98
 228 #define SRST_VIO0_AHB           99
 229 #define SRST_LCDC0_AXI          100
 230 #define SRST_LCDC0_AHB          101
 231 #define SRST_LCDC0_DCLK         102
 232 #define SRST_LCDC1_AXI          103
 233 #define SRST_LCDC1_AHB          104
 234 #define SRST_LCDC1_DCLK         105
 235 #define SRST_IPP_AXI            106
 236 #define SRST_IPP_AHB            107
 237 #define SRST_RGA_AXI            108
 238 #define SRST_RGA_AHB            109
 239 #define SRST_CIF0               110
 240
 241 #define SRST_VCODEC_AXI         112
 242 #define SRST_VCODEC_AHB         113
 243 #define SRST_VIO1_AXI           114
 244 #define SRST_VCODEC_CPU         115
 245 #define SRST_VCODEC_NIU         116
 246 #define SRST_GPU                120
 247 #define SRST_GPU_NIU            122
 248 #define SRST_TFUN_ATB           125
 249 #define SRST_TFUN_APB           126
 250 #define SRST_CTI4_APB           127
 251
 252 #define SRST_TPIU_APB           128
 253 #define SRST_TRACE              129
 254 #define SRST_CORE_DBG           130
 255 #define SRST_DBG_APB            131
 256 #define SRST_CTI0               132
 257 #define SRST_CTI0_APB           133
 258 #define SRST_CTI1               134
 259 #define SRST_CTI1_APB           135
 260 #define SRST_PTM_CORE0          136
 261 #define SRST_PTM_CORE1          137
 262 #define SRST_PTM0               138
 263 #define SRST_PTM0_ATB           139
 264 #define SRST_PTM1               140
 265 #define SRST_PTM1_ATB           141
 266 #define SRST_CTM                142
 267 #define SRST_TS                 143
 268
 269 #endif