include/exec/cpu-all.h

   1 /*
   2  * defines common to all virtual CPUs
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ALL_H
  20 #define CPU_ALL_H
  21
  22 #include "exec/page-protection.h"
  23 #include "exec/cpu-common.h"
  24 #include "exec/memory.h"
  25 #include "exec/tswap.h"
  26 #include "hw/core/cpu.h"
  27
  28 /* some important defines:
  29  *
  30  * HOST_BIG_ENDIAN : whether the host cpu is big endian and
  31  * otherwise little endian.
  32  *
  33  * TARGET_BIG_ENDIAN : same for the target cpu
  34  */
  35
  36 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
  37 #define BSWAP_NEEDED
  38 #endif
  39
  40 /* Target-endianness CPU memory access functions. These fit into the
  41  * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
  42  */
  43 #if TARGET_BIG_ENDIAN
  44 #define lduw_p(p) lduw_be_p(p)
  45 #define ldsw_p(p) ldsw_be_p(p)
  46 #define ldl_p(p) ldl_be_p(p)
  47 #define ldq_p(p) ldq_be_p(p)
  48 #define stw_p(p, v) stw_be_p(p, v)
  49 #define stl_p(p, v) stl_be_p(p, v)
  50 #define stq_p(p, v) stq_be_p(p, v)
  51 #define ldn_p(p, sz) ldn_be_p(p, sz)
  52 #define stn_p(p, sz, v) stn_be_p(p, sz, v)
  53 #else
  54 #define lduw_p(p) lduw_le_p(p)
  55 #define ldsw_p(p) ldsw_le_p(p)
  56 #define ldl_p(p) ldl_le_p(p)
  57 #define ldq_p(p) ldq_le_p(p)
  58 #define stw_p(p, v) stw_le_p(p, v)
  59 #define stl_p(p, v) stl_le_p(p, v)
  60 #define stq_p(p, v) stq_le_p(p, v)
  61 #define ldn_p(p, sz) ldn_le_p(p, sz)
  62 #define stn_p(p, sz, v) stn_le_p(p, sz, v)
  63 #endif
  64
  65 /* MMU memory access macros */
  66
  67 #if defined(CONFIG_USER_ONLY)
  68 #include "user/abitypes.h"
  69
  70 /*
  71  * If non-zero, the guest virtual address space is a contiguous subset
  72  * of the host virtual address space, i.e. '-R reserved_va' is in effect
  73  * either from the command-line or by default.  The value is the last
  74  * byte of the guest address space e.g. UINT32_MAX.
  75  *
  76  * If zero, the host and guest virtual address spaces are intermingled.
  77  */
  78 extern unsigned long reserved_va;
  79
  80 /*
  81  * Limit the guest addresses as best we can.
  82  *
  83  * When not using -R reserved_va, we cannot really limit the guest
  84  * to less address space than the host.  For 32-bit guests, this
  85  * acts as a sanity check that we're not giving the guest an address
  86  * that it cannot even represent.  For 64-bit guests... the address
  87  * might not be what the real kernel would give, but it is at least
  88  * representable in the guest.
  89  *
  90  * TODO: Improve address allocation to avoid this problem, and to
  91  * avoid setting bits at the top of guest addresses that might need
  92  * to be used for tags.
  93  */
  94 #define GUEST_ADDR_MAX_                                                 \
  95     ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ?  \
  96      UINT32_MAX : ~0ul)
  97 #define GUEST_ADDR_MAX    (reserved_va ? : GUEST_ADDR_MAX_)
  98
  99 #else
 100
 101 #include "exec/hwaddr.h"
 102
 103 #define SUFFIX
 104 #define ARG1         as
 105 #define ARG1_DECL    AddressSpace *as
 106 #define TARGET_ENDIANNESS
 107 #include "exec/memory_ldst.h.inc"
 108
 109 #define SUFFIX       _cached_slow
 110 #define ARG1         cache
 111 #define ARG1_DECL    MemoryRegionCache *cache
 112 #define TARGET_ENDIANNESS
 113 #include "exec/memory_ldst.h.inc"
 114
 115 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
 116 {
 117     address_space_stl_notdirty(as, addr, val,
 118                                MEMTXATTRS_UNSPECIFIED, NULL);
 119 }
 120
 121 #define SUFFIX
 122 #define ARG1         as
 123 #define ARG1_DECL    AddressSpace *as
 124 #define TARGET_ENDIANNESS
 125 #include "exec/memory_ldst_phys.h.inc"
 126
 127 /* Inline fast path for direct RAM access.  */
 128 #define ENDIANNESS
 129 #include "exec/memory_ldst_cached.h.inc"
 130
 131 #define SUFFIX       _cached
 132 #define ARG1         cache
 133 #define ARG1_DECL    MemoryRegionCache *cache
 134 #define TARGET_ENDIANNESS
 135 #include "exec/memory_ldst_phys.h.inc"
 136 #endif
 137
 138 /* page related stuff */
 139
 140 #ifdef TARGET_PAGE_BITS_VARY
 141 # include "exec/page-vary.h"
 142 extern const TargetPageBits target_page;
 143 # ifdef CONFIG_DEBUG_TCG
 144 #  define TARGET_PAGE_BITS   ({ assert(target_page.decided); \
 145                                 target_page.bits; })
 146 #  define TARGET_PAGE_MASK   ({ assert(target_page.decided); \
 147                                 (target_long)target_page.mask; })
 148 # else
 149 #  define TARGET_PAGE_BITS   target_page.bits
 150 #  define TARGET_PAGE_MASK   ((target_long)target_page.mask)
 151 # endif
 152 # define TARGET_PAGE_SIZE    (-(int)TARGET_PAGE_MASK)
 153 #else
 154 # define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
 155 # define TARGET_PAGE_SIZE    (1 << TARGET_PAGE_BITS)
 156 # define TARGET_PAGE_MASK    ((target_long)-1 << TARGET_PAGE_BITS)
 157 #endif
 158
 159 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
 160
 161 #if defined(CONFIG_USER_ONLY)
 162 void page_dump(FILE *f);
 163
 164 typedef int (*walk_memory_regions_fn)(void *, target_ulong,
 165                                       target_ulong, unsigned long);
 166 int walk_memory_regions(void *, walk_memory_regions_fn);
 167
 168 int page_get_flags(target_ulong address);
 169 void page_set_flags(target_ulong start, target_ulong last, int flags);
 170 void page_reset_target_data(target_ulong start, target_ulong last);
 171
 172 /**
 173  * page_check_range
 174  * @start: first byte of range
 175  * @len: length of range
 176  * @flags: flags required for each page
 177  *
 178  * Return true if every page in [@start, @start+@len) has @flags set.
 179  * Return false if any page is unmapped.  Thus testing flags == 0 is
 180  * equivalent to testing for flags == PAGE_VALID.
 181  */
 182 bool page_check_range(target_ulong start, target_ulong last, int flags);
 183
 184 /**
 185  * page_check_range_empty:
 186  * @start: first byte of range
 187  * @last: last byte of range
 188  * Context: holding mmap lock
 189  *
 190  * Return true if the entire range [@start, @last] is unmapped.
 191  * The memory lock must be held so that the caller will can ensure
 192  * the result stays true until a new mapping can be installed.
 193  */
 194 bool page_check_range_empty(target_ulong start, target_ulong last);
 195
 196 /**
 197  * page_find_range_empty
 198  * @min: first byte of search range
 199  * @max: last byte of search range
 200  * @len: size of the hole required
 201  * @align: alignment of the hole required (power of 2)
 202  *
 203  * If there is a range [x, x+@len) within [@min, @max] such that
 204  * x % @align == 0, then return x.  Otherwise return -1.
 205  * The memory lock must be held, as the caller will want to ensure
 206  * the returned range stays empty until a new mapping can be installed.
 207  */
 208 target_ulong page_find_range_empty(target_ulong min, target_ulong max,
 209                                    target_ulong len, target_ulong align);
 210
 211 /**
 212  * page_get_target_data(address)
 213  * @address: guest virtual address
 214  *
 215  * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate
 216  * with the guest page at @address, allocating it if necessary.  The
 217  * caller should already have verified that the address is valid.
 218  *
 219  * The memory will be freed when the guest page is deallocated,
 220  * e.g. with the munmap system call.
 221  */
 222 void *page_get_target_data(target_ulong address)
 223     __attribute__((returns_nonnull));
 224 #endif
 225
 226 CPUArchState *cpu_copy(CPUArchState *env);
 227
 228 /* Flags for use in ENV->INTERRUPT_PENDING.
 229
 230    The numbers assigned here are non-sequential in order to preserve
 231    binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
 232    previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
 233    the vmstate dump.  */
 234
 235 /* External hardware interrupt pending.  This is typically used for
 236    interrupts from devices.  */
 237 #define CPU_INTERRUPT_HARD        0x0002
 238
 239 /* Exit the current TB.  This is typically used when some system-level device
 240    makes some change to the memory mapping.  E.g. the a20 line change.  */
 241 #define CPU_INTERRUPT_EXITTB      0x0004
 242
 243 /* Halt the CPU.  */
 244 #define CPU_INTERRUPT_HALT        0x0020
 245
 246 /* Debug event pending.  */
 247 #define CPU_INTERRUPT_DEBUG       0x0080
 248
 249 /* Reset signal.  */
 250 #define CPU_INTERRUPT_RESET       0x0400
 251
 252 /* Several target-specific external hardware interrupts.  Each target/cpu.h
 253    should define proper names based on these defines.  */
 254 #define CPU_INTERRUPT_TGT_EXT_0   0x0008
 255 #define CPU_INTERRUPT_TGT_EXT_1   0x0010
 256 #define CPU_INTERRUPT_TGT_EXT_2   0x0040
 257 #define CPU_INTERRUPT_TGT_EXT_3   0x0200
 258 #define CPU_INTERRUPT_TGT_EXT_4   0x1000
 259
 260 /* Several target-specific internal interrupts.  These differ from the
 261    preceding target-specific interrupts in that they are intended to
 262    originate from within the cpu itself, typically in response to some
 263    instruction being executed.  These, therefore, are not masked while
 264    single-stepping within the debugger.  */
 265 #define CPU_INTERRUPT_TGT_INT_0   0x0100
 266 #define CPU_INTERRUPT_TGT_INT_1   0x0800
 267 #define CPU_INTERRUPT_TGT_INT_2   0x2000
 268
 269 /* First unused bit: 0x4000.  */
 270
 271 /* The set of all bits that should be masked when single-stepping.  */
 272 #define CPU_INTERRUPT_SSTEP_MASK \
 273     (CPU_INTERRUPT_HARD          \
 274      | CPU_INTERRUPT_TGT_EXT_0   \
 275      | CPU_INTERRUPT_TGT_EXT_1   \
 276      | CPU_INTERRUPT_TGT_EXT_2   \
 277      | CPU_INTERRUPT_TGT_EXT_3   \
 278      | CPU_INTERRUPT_TGT_EXT_4)
 279
 280 #ifdef CONFIG_USER_ONLY
 281
 282 /*
 283  * Allow some level of source compatibility with softmmu.  We do not
 284  * support any of the more exotic features, so only invalid pages may
 285  * be signaled by probe_access_flags().
 286  */
 287 #define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS_MIN - 1))
 288 #define TLB_MMIO            (1 << (TARGET_PAGE_BITS_MIN - 2))
 289 #define TLB_WATCHPOINT      0
 290
 291 static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
 292 {
 293     return MMU_USER_IDX;
 294 }
 295 #else
 296
 297 /*
 298  * Flags stored in the low bits of the TLB virtual address.
 299  * These are defined so that fast path ram access is all zeros.
 300  * The flags all must be between TARGET_PAGE_BITS and
 301  * maximum address alignment bit.
 302  *
 303  * Use TARGET_PAGE_BITS_MIN so that these bits are constant
 304  * when TARGET_PAGE_BITS_VARY is in effect.
 305  *
 306  * The count, if not the placement of these bits is known
 307  * to tcg/tcg-op-ldst.c, check_max_alignment().
 308  */
 309 /* Zero if TLB entry is valid.  */
 310 #define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS_MIN - 1))
 311 /* Set if TLB entry references a clean RAM page.  The iotlb entry will
 312    contain the page physical address.  */
 313 #define TLB_NOTDIRTY        (1 << (TARGET_PAGE_BITS_MIN - 2))
 314 /* Set if TLB entry is an IO callback.  */
 315 #define TLB_MMIO            (1 << (TARGET_PAGE_BITS_MIN - 3))
 316 /* Set if TLB entry writes ignored.  */
 317 #define TLB_DISCARD_WRITE   (1 << (TARGET_PAGE_BITS_MIN - 4))
 318 /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
 319 #define TLB_FORCE_SLOW      (1 << (TARGET_PAGE_BITS_MIN - 5))
 320
 321 /*
 322  * Use this mask to check interception with an alignment mask
 323  * in a TCG backend.
 324  */
 325 #define TLB_FLAGS_MASK \
 326     (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
 327     | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
 328
 329 /*
 330  * Flags stored in CPUTLBEntryFull.slow_flags[x].
 331  * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
 332  */
 333 /* Set if TLB entry requires byte swap.  */
 334 #define TLB_BSWAP            (1 << 0)
 335 /* Set if TLB entry contains a watchpoint.  */
 336 #define TLB_WATCHPOINT       (1 << 1)
 337 /* Set if TLB entry requires aligned accesses.  */
 338 #define TLB_CHECK_ALIGNED    (1 << 2)
 339
 340 #define TLB_SLOW_FLAGS_MASK  (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
 341
 342 /* The two sets of flags must not overlap. */
 343 QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
 344
 345 /**
 346  * tlb_hit_page: return true if page aligned @addr is a hit against the
 347  * TLB entry @tlb_addr
 348  *
 349  * @addr: virtual address to test (must be page aligned)
 350  * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
 351  */
 352 static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
 353 {
 354     return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
 355 }
 356
 357 /**
 358  * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
 359  *
 360  * @addr: virtual address to test (need not be page aligned)
 361  * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
 362  */
 363 static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
 364 {
 365     return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
 366 }
 367
 368 #endif /* !CONFIG_USER_ONLY */
 369
 370 /* Validate correct placement of CPUArchState. */
 371 #include "cpu.h"
 372 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
 373 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
 374
 375 #endif /* CPU_ALL_H */