4 /* CPU interfaces that are target independent. */
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/hwaddr.h"
12 * Type wide enough to contain any #target_ulong virtual address.
14 typedef uint64_t vaddr
;
15 #define VADDR_PRId PRId64
16 #define VADDR_PRIu PRIu64
17 #define VADDR_PRIo PRIo64
18 #define VADDR_PRIx PRIx64
19 #define VADDR_PRIX PRIX64
20 #define VADDR_MAX UINT64_MAX
22 void cpu_exec_init_all(void);
23 void cpu_exec_step_atomic(CPUState
*cpu
);
25 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
26 * when intptr_t is 32-bit and we are aligning a long long.
28 extern uintptr_t qemu_host_page_size
;
29 extern intptr_t qemu_host_page_mask
;
31 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
32 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
34 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
35 extern QemuMutex qemu_cpu_list_lock
;
36 void qemu_init_cpu_list(void);
37 void cpu_list_lock(void);
38 void cpu_list_unlock(void);
39 unsigned int cpu_list_generation_id_get(void);
41 void tcg_flush_softmmu_tlb(CPUState
*cs
);
42 void tcg_flush_jmp_cache(CPUState
*cs
);
44 void tcg_iommu_init_notifier_list(CPUState
*cpu
);
45 void tcg_iommu_free_notifier_list(CPUState
*cpu
);
47 #if !defined(CONFIG_USER_ONLY)
56 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
58 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
61 /* address in the RAM (different from a physical address) */
62 #if defined(CONFIG_XEN_BACKEND)
63 typedef uint64_t ram_addr_t
;
64 # define RAM_ADDR_MAX UINT64_MAX
65 # define RAM_ADDR_FMT "%" PRIx64
67 typedef uintptr_t ram_addr_t
;
68 # define RAM_ADDR_MAX UINTPTR_MAX
69 # define RAM_ADDR_FMT "%" PRIxPTR
74 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
);
75 /* This should not be used by devices. */
76 ram_addr_t
qemu_ram_addr_from_host(void *ptr
);
77 ram_addr_t
qemu_ram_addr_from_host_nofail(void *ptr
);
78 RAMBlock
*qemu_ram_block_by_name(const char *name
);
79 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
81 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
);
82 void qemu_ram_set_idstr(RAMBlock
*block
, const char *name
, DeviceState
*dev
);
83 void qemu_ram_unset_idstr(RAMBlock
*block
);
84 const char *qemu_ram_get_idstr(RAMBlock
*rb
);
85 void *qemu_ram_get_host_addr(RAMBlock
*rb
);
86 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
);
87 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
);
88 ram_addr_t
qemu_ram_get_max_length(RAMBlock
*rb
);
89 bool qemu_ram_is_shared(RAMBlock
*rb
);
90 bool qemu_ram_is_noreserve(RAMBlock
*rb
);
91 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
);
92 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
);
93 bool qemu_ram_is_migratable(RAMBlock
*rb
);
94 void qemu_ram_set_migratable(RAMBlock
*rb
);
95 void qemu_ram_unset_migratable(RAMBlock
*rb
);
96 bool qemu_ram_is_named_file(RAMBlock
*rb
);
97 int qemu_ram_get_fd(RAMBlock
*rb
);
99 size_t qemu_ram_pagesize(RAMBlock
*block
);
100 size_t qemu_ram_pagesize_largest(void);
103 * cpu_address_space_init:
104 * @cpu: CPU to add this address space to
105 * @asidx: integer index of this address space
106 * @prefix: prefix to be used as name of address space
107 * @mr: the root memory region of address space
109 * Add the specified address space to the CPU's cpu_ases list.
110 * The address space added with @asidx 0 is the one used for the
111 * convenience pointer cpu->as.
112 * The target-specific code which registers ASes is responsible
113 * for defining what semantics address space 0, 1, 2, etc have.
115 * Before the first call to this function, the caller must set
116 * cpu->num_ases to the total number of address spaces it needs
119 * Note that with KVM only one address space is supported.
121 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
122 const char *prefix
, MemoryRegion
*mr
);
124 void cpu_physical_memory_rw(hwaddr addr
, void *buf
,
125 hwaddr len
, bool is_write
);
126 static inline void cpu_physical_memory_read(hwaddr addr
,
127 void *buf
, hwaddr len
)
129 cpu_physical_memory_rw(addr
, buf
, len
, false);
131 static inline void cpu_physical_memory_write(hwaddr addr
,
132 const void *buf
, hwaddr len
)
134 cpu_physical_memory_rw(addr
, (void *)buf
, len
, true);
136 void cpu_reloading_memory_map(void);
137 void *cpu_physical_memory_map(hwaddr addr
,
140 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
141 bool is_write
, hwaddr access_len
);
142 void cpu_register_map_client(QEMUBH
*bh
);
143 void cpu_unregister_map_client(QEMUBH
*bh
);
145 bool cpu_physical_memory_is_io(hwaddr phys_addr
);
147 /* Coalesced MMIO regions are areas where write operations can be reordered.
148 * This usually implies that write operations are side-effect free. This allows
149 * batching which can make a major impact on performance when using
152 void qemu_flush_coalesced_mmio_buffer(void);
154 void cpu_flush_icache_range(hwaddr start
, hwaddr len
);
156 typedef int (RAMBlockIterFunc
)(RAMBlock
*rb
, void *opaque
);
158 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
);
159 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
);
163 /* Returns: 0 on success, -1 on error */
164 int cpu_memory_rw_debug(CPUState
*cpu
, vaddr addr
,
165 void *ptr
, size_t len
, bool is_write
);
168 void list_cpus(void);
170 #endif /* CPU_COMMON_H */