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git.proxmox.com Git - mirror_qemu.git/blob - include/exec/cpu-defs.h
2 * common defines for all CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #error cpu.h included from common code
28 #include "qemu/osdep.h"
29 #include "qemu/queue.h"
30 #ifndef CONFIG_USER_ONLY
31 #include "exec/hwaddr.h"
34 #ifndef TARGET_LONG_BITS
35 #error TARGET_LONG_BITS must be defined before including this header
38 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
40 /* target_ulong is the type of a virtual address */
41 #if TARGET_LONG_SIZE == 4
42 typedef int32_t target_long
;
43 typedef uint32_t target_ulong
;
44 #define TARGET_FMT_lx "%08x"
45 #define TARGET_FMT_ld "%d"
46 #define TARGET_FMT_lu "%u"
47 #elif TARGET_LONG_SIZE == 8
48 typedef int64_t target_long
;
49 typedef uint64_t target_ulong
;
50 #define TARGET_FMT_lx "%016" PRIx64
51 #define TARGET_FMT_ld "%" PRId64
52 #define TARGET_FMT_lu "%" PRIu64
54 #error TARGET_LONG_SIZE undefined
57 #define EXCP_INTERRUPT 0x10000 /* async interruption */
58 #define EXCP_HLT 0x10001 /* hlt instruction reached */
59 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
60 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
61 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
63 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
64 addresses on the same page. The top bits are the same. This allows
65 TLB invalidation to quickly clear a subset of the hash table. */
66 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
67 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
68 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
69 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
71 #if !defined(CONFIG_USER_ONLY)
72 #define CPU_TLB_BITS 8
73 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
74 /* use a fully associative victim tlb of 8 entries */
75 #define CPU_VTLB_SIZE 8
77 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
78 #define CPU_TLB_ENTRY_BITS 4
80 #define CPU_TLB_ENTRY_BITS 5
83 typedef struct CPUTLBEntry
{
84 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
85 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
87 bit 3 : indicates that the entry is invalid
90 target_ulong addr_read
;
91 target_ulong addr_write
;
92 target_ulong addr_code
;
93 /* Addend to virtual address to get host address. IO accesses
94 use the corresponding iotlb value. */
96 /* padding to get a power of two size */
97 uint8_t dummy
[(1 << CPU_TLB_ENTRY_BITS
) -
98 (sizeof(target_ulong
) * 3 +
99 ((-sizeof(target_ulong
) * 3) & (sizeof(uintptr_t) - 1)) +
103 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry
) != (1 << CPU_TLB_ENTRY_BITS
));
105 #define CPU_COMMON_TLB \
106 /* The meaning of the MMU modes is defined in the target code. */ \
107 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
108 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
109 hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
110 hwaddr iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \
111 target_ulong tlb_flush_addr; \
112 target_ulong tlb_flush_mask; \
113 target_ulong vtlb_index; \
117 #define CPU_COMMON_TLB
122 #define CPU_TEMP_BUF_NLONGS 128
124 /* soft mmu support */ \