include/exec/cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "qemu/host-utils.h"
  27 #include "qemu/thread.h"
  28 #ifndef CONFIG_USER_ONLY
  29 #include "exec/hwaddr.h"
  30 #endif
  31 #include "exec/memattrs.h"
  32 #include "hw/core/cpu.h"
  33
  34 #include "cpu-param.h"
  35
  36 #ifndef TARGET_LONG_BITS
  37 # error TARGET_LONG_BITS must be defined in cpu-param.h
  38 #endif
  39 #ifndef TARGET_PHYS_ADDR_SPACE_BITS
  40 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
  41 #endif
  42 #ifndef TARGET_VIRT_ADDR_SPACE_BITS
  43 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h
  44 #endif
  45 #ifndef TARGET_PAGE_BITS
  46 # ifdef TARGET_PAGE_BITS_VARY
  47 #  ifndef TARGET_PAGE_BITS_MIN
  48 #   error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
  49 #  endif
  50 # else
  51 #  error TARGET_PAGE_BITS must be defined in cpu-param.h
  52 # endif
  53 #endif
  54
  55 #include "exec/target_long.h"
  56
  57 /*
  58  * Fix the number of mmu modes to 16, which is also the maximum
  59  * supported by the softmmu tlb api.
  60  */
  61 #define NB_MMU_MODES 16
  62
  63 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  64
  65 /* use a fully associative victim tlb of 8 entries */
  66 #define CPU_VTLB_SIZE 8
  67
  68 #define CPU_TLB_ENTRY_BITS 5
  69
  70 #define CPU_TLB_DYN_MIN_BITS 6
  71 #define CPU_TLB_DYN_DEFAULT_BITS 8
  72
  73 # if HOST_LONG_BITS == 32
  74 /* Make sure we do not require a double-word shift for the TLB load */
  75 #  define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
  76 # else /* HOST_LONG_BITS == 64 */
  77 /*
  78  * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
  79  * 2**34 == 16G of address space. This is roughly what one would expect a
  80  * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
  81  * Skylake's Level-2 STLB has 16 1G entries.
  82  * Also, make sure we do not size the TLB past the guest's address space.
  83  */
  84 #  ifdef TARGET_PAGE_BITS_VARY
  85 #   define CPU_TLB_DYN_MAX_BITS                                  \
  86     MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
  87 #  else
  88 #   define CPU_TLB_DYN_MAX_BITS                                  \
  89     MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
  90 #  endif
  91 # endif
  92
  93 /* Minimalized TLB entry for use by TCG fast path. */
  94 typedef union CPUTLBEntry {
  95     struct {
  96         uint64_t addr_read;
  97         uint64_t addr_write;
  98         uint64_t addr_code;
  99         /*
 100          * Addend to virtual address to get host address.  IO accesses
 101          * use the corresponding iotlb value.
 102          */
 103         uintptr_t addend;
 104     };
 105     /*
 106      * Padding to get a power of two size, as well as index
 107      * access to addr_{read,write,code}.
 108      */
 109     uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)];
 110 } CPUTLBEntry;
 111
 112 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
 113
 114 #endif  /* !CONFIG_USER_ONLY && CONFIG_TCG */
 115
 116 #if !defined(CONFIG_USER_ONLY)
 117 /*
 118  * The full TLB entry, which is not accessed by generated TCG code,
 119  * so the layout is not as critical as that of CPUTLBEntry. This is
 120  * also why we don't want to combine the two structs.
 121  */
 122 typedef struct CPUTLBEntryFull {
 123     /*
 124      * @xlat_section contains:
 125      *  - in the lower TARGET_PAGE_BITS, a physical section number
 126      *  - with the lower TARGET_PAGE_BITS masked off, an offset which
 127      *    must be added to the virtual address to obtain:
 128      *     + the ram_addr_t of the target RAM (if the physical section
 129      *       number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
 130      *     + the offset within the target MemoryRegion (otherwise)
 131      */
 132     hwaddr xlat_section;
 133
 134     /*
 135      * @phys_addr contains the physical address in the address space
 136      * given by cpu_asidx_from_attrs(cpu, @attrs).
 137      */
 138     hwaddr phys_addr;
 139
 140     /* @attrs contains the memory transaction attributes for the page. */
 141     MemTxAttrs attrs;
 142
 143     /* @prot contains the complete protections for the page. */
 144     uint8_t prot;
 145
 146     /* @lg_page_size contains the log2 of the page size. */
 147     uint8_t lg_page_size;
 148
 149     /*
 150      * Allow target-specific additions to this structure.
 151      * This may be used to cache items from the guest cpu
 152      * page tables for later use by the implementation.
 153      */
 154 #ifdef TARGET_PAGE_ENTRY_EXTRA
 155     TARGET_PAGE_ENTRY_EXTRA
 156 #endif
 157 } CPUTLBEntryFull;
 158 #endif  /* !CONFIG_USER_ONLY */
 159
 160 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 161 /*
 162  * Data elements that are per MMU mode, minus the bits accessed by
 163  * the TCG fast path.
 164  */
 165 typedef struct CPUTLBDesc {
 166     /*
 167      * Describe a region covering all of the large pages allocated
 168      * into the tlb.  When any page within this region is flushed,
 169      * we must flush the entire tlb.  The region is matched if
 170      * (addr & large_page_mask) == large_page_addr.
 171      */
 172     target_ulong large_page_addr;
 173     target_ulong large_page_mask;
 174     /* host time (in ns) at the beginning of the time window */
 175     int64_t window_begin_ns;
 176     /* maximum number of entries observed in the window */
 177     size_t window_max_entries;
 178     size_t n_used_entries;
 179     /* The next index to use in the tlb victim table.  */
 180     size_t vindex;
 181     /* The tlb victim table, in two parts.  */
 182     CPUTLBEntry vtable[CPU_VTLB_SIZE];
 183     CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE];
 184     CPUTLBEntryFull *fulltlb;
 185 } CPUTLBDesc;
 186
 187 /*
 188  * Data elements that are per MMU mode, accessed by the fast path.
 189  * The structure is aligned to aid loading the pair with one insn.
 190  */
 191 typedef struct CPUTLBDescFast {
 192     /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
 193     uintptr_t mask;
 194     /* The array of tlb entries itself. */
 195     CPUTLBEntry *table;
 196 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *));
 197
 198 /*
 199  * Data elements that are shared between all MMU modes.
 200  */
 201 typedef struct CPUTLBCommon {
 202     /* Serialize updates to f.table and d.vtable, and others as noted. */
 203     QemuSpin lock;
 204     /*
 205      * Within dirty, for each bit N, modifications have been made to
 206      * mmu_idx N since the last time that mmu_idx was flushed.
 207      * Protected by tlb_c.lock.
 208      */
 209     uint16_t dirty;
 210     /*
 211      * Statistics.  These are not lock protected, but are read and
 212      * written atomically.  This allows the monitor to print a snapshot
 213      * of the stats without interfering with the cpu.
 214      */
 215     size_t full_flush_count;
 216     size_t part_flush_count;
 217     size_t elide_flush_count;
 218 } CPUTLBCommon;
 219
 220 /*
 221  * The entire softmmu tlb, for all MMU modes.
 222  * The meaning of each of the MMU modes is defined in the target code.
 223  * Since this is placed within CPUNegativeOffsetState, the smallest
 224  * negative offsets are at the end of the struct.
 225  */
 226
 227 typedef struct CPUTLB {
 228     CPUTLBCommon c;
 229     CPUTLBDesc d[NB_MMU_MODES];
 230     CPUTLBDescFast f[NB_MMU_MODES];
 231 } CPUTLB;
 232
 233 /* This will be used by TCG backends to compute offsets.  */
 234 #define TLB_MASK_TABLE_OFS(IDX) \
 235     ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env))
 236
 237 #else
 238
 239 typedef struct CPUTLB { } CPUTLB;
 240
 241 #endif  /* !CONFIG_USER_ONLY && CONFIG_TCG */
 242
 243 /*
 244  * This structure must be placed in ArchCPU immediately
 245  * before CPUArchState, as a field named "neg".
 246  */
 247 typedef struct CPUNegativeOffsetState {
 248     CPUTLB tlb;
 249     IcountDecr icount_decr;
 250 } CPUNegativeOffsetState;
 251
 252 #endif