include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef EXEC_ALL_H
  21 #define EXEC_ALL_H
  22
  23 #include "cpu.h"
  24 #ifdef CONFIG_TCG
  25 #include "exec/cpu_ldst.h"
  26 #endif
  27
  28 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  29 #define DEBUG_DISAS
  30
  31 /* Page tracking code uses ram addresses in system mode, and virtual
  32    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  33    type.  */
  34 #if defined(CONFIG_USER_ONLY)
  35 typedef abi_ulong tb_page_addr_t;
  36 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
  37 #else
  38 typedef ram_addr_t tb_page_addr_t;
  39 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
  40 #endif
  41
  42 /**
  43  * cpu_restore_state:
  44  * @cpu: the vCPU state is to be restore to
  45  * @searched_pc: the host PC the fault occurred at
  46  * @will_exit: true if the TB executed will be interrupted after some
  47                cpu adjustments. Required for maintaining the correct
  48                icount valus
  49  * @return: true if state was restored, false otherwise
  50  *
  51  * Attempt to restore the state for a fault occurring in translated
  52  * code. If the searched_pc is not in translated code no state is
  53  * restored and the function returns false.
  54  */
  55 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
  56
  57 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
  58 G_NORETURN void cpu_loop_exit(CPUState *cpu);
  59 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  60 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
  61
  62 /**
  63  * cpu_loop_exit_requested:
  64  * @cpu: The CPU state to be tested
  65  *
  66  * Indicate if somebody asked for a return of the CPU to the main loop
  67  * (e.g., via cpu_exit() or cpu_interrupt()).
  68  *
  69  * This is helpful for architectures that support interruptible
  70  * instructions. After writing back all state to registers/memory, this
  71  * call can be used to check if it makes sense to return to the main loop
  72  * or to continue executing the interruptible instruction.
  73  */
  74 static inline bool cpu_loop_exit_requested(CPUState *cpu)
  75 {
  76     return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0;
  77 }
  78
  79 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  80 /* cputlb.c */
  81 /**
  82  * tlb_init - initialize a CPU's TLB
  83  * @cpu: CPU whose TLB should be initialized
  84  */
  85 void tlb_init(CPUState *cpu);
  86 /**
  87  * tlb_destroy - destroy a CPU's TLB
  88  * @cpu: CPU whose TLB should be destroyed
  89  */
  90 void tlb_destroy(CPUState *cpu);
  91 /**
  92  * tlb_flush_page:
  93  * @cpu: CPU whose TLB should be flushed
  94  * @addr: virtual address of page to be flushed
  95  *
  96  * Flush one page from the TLB of the specified CPU, for all
  97  * MMU indexes.
  98  */
  99 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 100 /**
 101  * tlb_flush_page_all_cpus:
 102  * @cpu: src CPU of the flush
 103  * @addr: virtual address of page to be flushed
 104  *
 105  * Flush one page from the TLB of the specified CPU, for all
 106  * MMU indexes.
 107  */
 108 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
 109 /**
 110  * tlb_flush_page_all_cpus_synced:
 111  * @cpu: src CPU of the flush
 112  * @addr: virtual address of page to be flushed
 113  *
 114  * Flush one page from the TLB of the specified CPU, for all MMU
 115  * indexes like tlb_flush_page_all_cpus except the source vCPUs work
 116  * is scheduled as safe work meaning all flushes will be complete once
 117  * the source vCPUs safe work is complete. This will depend on when
 118  * the guests translation ends the TB.
 119  */
 120 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
 121 /**
 122  * tlb_flush:
 123  * @cpu: CPU whose TLB should be flushed
 124  *
 125  * Flush the entire TLB for the specified CPU. Most CPU architectures
 126  * allow the implementation to drop entries from the TLB at any time
 127  * so this is generally safe. If more selective flushing is required
 128  * use one of the other functions for efficiency.
 129  */
 130 void tlb_flush(CPUState *cpu);
 131 /**
 132  * tlb_flush_all_cpus:
 133  * @cpu: src CPU of the flush
 134  */
 135 void tlb_flush_all_cpus(CPUState *src_cpu);
 136 /**
 137  * tlb_flush_all_cpus_synced:
 138  * @cpu: src CPU of the flush
 139  *
 140  * Like tlb_flush_all_cpus except this except the source vCPUs work is
 141  * scheduled as safe work meaning all flushes will be complete once
 142  * the source vCPUs safe work is complete. This will depend on when
 143  * the guests translation ends the TB.
 144  */
 145 void tlb_flush_all_cpus_synced(CPUState *src_cpu);
 146 /**
 147  * tlb_flush_page_by_mmuidx:
 148  * @cpu: CPU whose TLB should be flushed
 149  * @addr: virtual address of page to be flushed
 150  * @idxmap: bitmap of MMU indexes to flush
 151  *
 152  * Flush one page from the TLB of the specified CPU, for the specified
 153  * MMU indexes.
 154  */
 155 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
 156                               uint16_t idxmap);
 157 /**
 158  * tlb_flush_page_by_mmuidx_all_cpus:
 159  * @cpu: Originating CPU of the flush
 160  * @addr: virtual address of page to be flushed
 161  * @idxmap: bitmap of MMU indexes to flush
 162  *
 163  * Flush one page from the TLB of all CPUs, for the specified
 164  * MMU indexes.
 165  */
 166 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 167                                        uint16_t idxmap);
 168 /**
 169  * tlb_flush_page_by_mmuidx_all_cpus_synced:
 170  * @cpu: Originating CPU of the flush
 171  * @addr: virtual address of page to be flushed
 172  * @idxmap: bitmap of MMU indexes to flush
 173  *
 174  * Flush one page from the TLB of all CPUs, for the specified MMU
 175  * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
 176  * vCPUs work is scheduled as safe work meaning all flushes will be
 177  * complete once  the source vCPUs safe work is complete. This will
 178  * depend on when the guests translation ends the TB.
 179  */
 180 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 181                                               uint16_t idxmap);
 182 /**
 183  * tlb_flush_by_mmuidx:
 184  * @cpu: CPU whose TLB should be flushed
 185  * @wait: If true ensure synchronisation by exiting the cpu_loop
 186  * @idxmap: bitmap of MMU indexes to flush
 187  *
 188  * Flush all entries from the TLB of the specified CPU, for the specified
 189  * MMU indexes.
 190  */
 191 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
 192 /**
 193  * tlb_flush_by_mmuidx_all_cpus:
 194  * @cpu: Originating CPU of the flush
 195  * @idxmap: bitmap of MMU indexes to flush
 196  *
 197  * Flush all entries from all TLBs of all CPUs, for the specified
 198  * MMU indexes.
 199  */
 200 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
 201 /**
 202  * tlb_flush_by_mmuidx_all_cpus_synced:
 203  * @cpu: Originating CPU of the flush
 204  * @idxmap: bitmap of MMU indexes to flush
 205  *
 206  * Flush all entries from all TLBs of all CPUs, for the specified
 207  * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
 208  * vCPUs work is scheduled as safe work meaning all flushes will be
 209  * complete once  the source vCPUs safe work is complete. This will
 210  * depend on when the guests translation ends the TB.
 211  */
 212 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
 213
 214 /**
 215  * tlb_flush_page_bits_by_mmuidx
 216  * @cpu: CPU whose TLB should be flushed
 217  * @addr: virtual address of page to be flushed
 218  * @idxmap: bitmap of mmu indexes to flush
 219  * @bits: number of significant bits in address
 220  *
 221  * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
 222  */
 223 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
 224                                    uint16_t idxmap, unsigned bits);
 225
 226 /* Similarly, with broadcast and syncing. */
 227 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 228                                             uint16_t idxmap, unsigned bits);
 229 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
 230     (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
 231
 232 /**
 233  * tlb_flush_range_by_mmuidx
 234  * @cpu: CPU whose TLB should be flushed
 235  * @addr: virtual address of the start of the range to be flushed
 236  * @len: length of range to be flushed
 237  * @idxmap: bitmap of mmu indexes to flush
 238  * @bits: number of significant bits in address
 239  *
 240  * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
 241  * comparing only the low @bits worth of each virtual page.
 242  */
 243 void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 244                                target_ulong len, uint16_t idxmap,
 245                                unsigned bits);
 246
 247 /* Similarly, with broadcast and syncing. */
 248 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 249                                         target_ulong len, uint16_t idxmap,
 250                                         unsigned bits);
 251 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 252                                                target_ulong addr,
 253                                                target_ulong len,
 254                                                uint16_t idxmap,
 255                                                unsigned bits);
 256
 257 /**
 258  * tlb_set_page_full:
 259  * @cpu: CPU context
 260  * @mmu_idx: mmu index of the tlb to modify
 261  * @vaddr: virtual address of the entry to add
 262  * @full: the details of the tlb entry
 263  *
 264  * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
 265  * @full must be filled, except for xlat_section, and constitute
 266  * the complete description of the translated page.
 267  *
 268  * This is generally called by the target tlb_fill function after
 269  * having performed a successful page table walk to find the physical
 270  * address and attributes for the translation.
 271  *
 272  * At most one entry for a given virtual address is permitted. Only a
 273  * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
 274  * used by tlb_flush_page.
 275  */
 276 void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
 277                        CPUTLBEntryFull *full);
 278
 279 /**
 280  * tlb_set_page_with_attrs:
 281  * @cpu: CPU to add this TLB entry for
 282  * @vaddr: virtual address of page to add entry for
 283  * @paddr: physical address of the page
 284  * @attrs: memory transaction attributes
 285  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 286  * @mmu_idx: MMU index to insert TLB entry for
 287  * @size: size of the page in bytes
 288  *
 289  * Add an entry to this CPU's TLB (a mapping from virtual address
 290  * @vaddr to physical address @paddr) with the specified memory
 291  * transaction attributes. This is generally called by the target CPU
 292  * specific code after it has been called through the tlb_fill()
 293  * entry point and performed a successful page table walk to find
 294  * the physical address and attributes for the virtual address
 295  * which provoked the TLB miss.
 296  *
 297  * At most one entry for a given virtual address is permitted. Only a
 298  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 299  * used by tlb_flush_page.
 300  */
 301 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 302                              hwaddr paddr, MemTxAttrs attrs,
 303                              int prot, int mmu_idx, target_ulong size);
 304 /* tlb_set_page:
 305  *
 306  * This function is equivalent to calling tlb_set_page_with_attrs()
 307  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 308  * as a convenience for CPUs which don't use memory transaction attributes.
 309  */
 310 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 311                   hwaddr paddr, int prot,
 312                   int mmu_idx, target_ulong size);
 313 #else
 314 static inline void tlb_init(CPUState *cpu)
 315 {
 316 }
 317 static inline void tlb_destroy(CPUState *cpu)
 318 {
 319 }
 320 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 321 {
 322 }
 323 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
 324 {
 325 }
 326 static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
 327                                                   target_ulong addr)
 328 {
 329 }
 330 static inline void tlb_flush(CPUState *cpu)
 331 {
 332 }
 333 static inline void tlb_flush_all_cpus(CPUState *src_cpu)
 334 {
 335 }
 336 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
 337 {
 338 }
 339 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 340                                             target_ulong addr, uint16_t idxmap)
 341 {
 342 }
 343
 344 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
 345 {
 346 }
 347 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
 348                                                      target_ulong addr,
 349                                                      uint16_t idxmap)
 350 {
 351 }
 352 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
 353                                                             target_ulong addr,
 354                                                             uint16_t idxmap)
 355 {
 356 }
 357 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
 358 {
 359 }
 360
 361 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
 362                                                        uint16_t idxmap)
 363 {
 364 }
 365 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
 366                                                  target_ulong addr,
 367                                                  uint16_t idxmap,
 368                                                  unsigned bits)
 369 {
 370 }
 371 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
 372                                                           target_ulong addr,
 373                                                           uint16_t idxmap,
 374                                                           unsigned bits)
 375 {
 376 }
 377 static inline void
 378 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 379                                               uint16_t idxmap, unsigned bits)
 380 {
 381 }
 382 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 383                                              target_ulong len, uint16_t idxmap,
 384                                              unsigned bits)
 385 {
 386 }
 387 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
 388                                                       target_ulong addr,
 389                                                       target_ulong len,
 390                                                       uint16_t idxmap,
 391                                                       unsigned bits)
 392 {
 393 }
 394 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 395                                                              target_ulong addr,
 396                                                              target_long len,
 397                                                              uint16_t idxmap,
 398                                                              unsigned bits)
 399 {
 400 }
 401 #endif
 402 /**
 403  * probe_access:
 404  * @env: CPUArchState
 405  * @addr: guest virtual address to look up
 406  * @size: size of the access
 407  * @access_type: read, write or execute permission
 408  * @mmu_idx: MMU index to use for lookup
 409  * @retaddr: return address for unwinding
 410  *
 411  * Look up the guest virtual address @addr.  Raise an exception if the
 412  * page does not satisfy @access_type.  Raise an exception if the
 413  * access (@addr, @size) hits a watchpoint.  For writes, mark a clean
 414  * page as dirty.
 415  *
 416  * Finally, return the host address for a page that is backed by RAM,
 417  * or NULL if the page requires I/O.
 418  */
 419 void *probe_access(CPUArchState *env, target_ulong addr, int size,
 420                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 421
 422 static inline void *probe_write(CPUArchState *env, target_ulong addr, int size,
 423                                 int mmu_idx, uintptr_t retaddr)
 424 {
 425     return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
 426 }
 427
 428 static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
 429                                int mmu_idx, uintptr_t retaddr)
 430 {
 431     return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
 432 }
 433
 434 /**
 435  * probe_access_flags:
 436  * @env: CPUArchState
 437  * @addr: guest virtual address to look up
 438  * @access_type: read, write or execute permission
 439  * @mmu_idx: MMU index to use for lookup
 440  * @nonfault: suppress the fault
 441  * @phost: return value for host address
 442  * @retaddr: return address for unwinding
 443  *
 444  * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
 445  * the page, and storing the host address for RAM in @phost.
 446  *
 447  * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
 448  * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
 449  * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
 450  * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
 451  */
 452 int probe_access_flags(CPUArchState *env, target_ulong addr,
 453                        MMUAccessType access_type, int mmu_idx,
 454                        bool nonfault, void **phost, uintptr_t retaddr);
 455
 456 #ifndef CONFIG_USER_ONLY
 457 /**
 458  * probe_access_full:
 459  * Like probe_access_flags, except also return into @pfull.
 460  *
 461  * The CPUTLBEntryFull structure returned via @pfull is transient
 462  * and must be consumed or copied immediately, before any further
 463  * access or changes to TLB @mmu_idx.
 464  */
 465 int probe_access_full(CPUArchState *env, target_ulong addr,
 466                       MMUAccessType access_type, int mmu_idx,
 467                       bool nonfault, void **phost,
 468                       CPUTLBEntryFull **pfull, uintptr_t retaddr);
 469 #endif
 470
 471 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 472
 473 /* Estimated block size for TB allocation.  */
 474 /* ??? The following is based on a 2015 survey of x86_64 host output.
 475    Better would seem to be some sort of dynamically sized TB array,
 476    adapting to the block sizes actually being produced.  */
 477 #if defined(CONFIG_SOFTMMU)
 478 #define CODE_GEN_AVG_BLOCK_SIZE 400
 479 #else
 480 #define CODE_GEN_AVG_BLOCK_SIZE 150
 481 #endif
 482
 483 /*
 484  * Translation Cache-related fields of a TB.
 485  * This struct exists just for convenience; we keep track of TB's in a binary
 486  * search tree, and the only fields needed to compare TB's in the tree are
 487  * @ptr and @size.
 488  * Note: the address of search data can be obtained by adding @size to @ptr.
 489  */
 490 struct tb_tc {
 491     const void *ptr;    /* pointer to the translated code */
 492     size_t size;
 493 };
 494
 495 struct TranslationBlock {
 496 #if !TARGET_TB_PCREL
 497     /*
 498      * Guest PC corresponding to this block.  This must be the true
 499      * virtual address.  Therefore e.g. x86 stores EIP + CS_BASE, and
 500      * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
 501      * privilege, must store those bits elsewhere.
 502      *
 503      * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
 504      * written such that the TB is associated only with the physical
 505      * page and may be run in any virtual address context.  In this case,
 506      * PC must always be taken from ENV in a target-specific manner.
 507      * Unwind information is taken as offsets from the page, to be
 508      * deposited into the "current" PC.
 509      */
 510     target_ulong pc;
 511 #endif
 512
 513     /*
 514      * Target-specific data associated with the TranslationBlock, e.g.:
 515      * x86: the original user, the Code Segment virtual base,
 516      * arm: an extension of tb->flags,
 517      * s390x: instruction data for EXECUTE,
 518      * sparc: the next pc of the instruction queue (for delay slots).
 519      */
 520     target_ulong cs_base;
 521
 522     uint32_t flags; /* flags defining in which context the code was generated */
 523     uint32_t cflags;    /* compile flags */
 524
 525 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */
 526 #define CF_COUNT_MASK    0x000001ff
 527 #define CF_NO_GOTO_TB    0x00000200 /* Do not chain with goto_tb */
 528 #define CF_NO_GOTO_PTR   0x00000400 /* Do not chain with goto_ptr */
 529 #define CF_SINGLE_STEP   0x00000800 /* gdbstub single-step in effect */
 530 #define CF_LAST_IO       0x00008000 /* Last insn may be an IO access.  */
 531 #define CF_MEMI_ONLY     0x00010000 /* Only instrument memory ops */
 532 #define CF_USE_ICOUNT    0x00020000
 533 #define CF_INVALID       0x00040000 /* TB is stale. Set with @jmp_lock held */
 534 #define CF_PARALLEL      0x00080000 /* Generate code for a parallel context */
 535 #define CF_NOIRQ         0x00100000 /* Generate an uninterruptible TB */
 536 #define CF_CLUSTER_MASK  0xff000000 /* Top 8 bits are cluster ID */
 537 #define CF_CLUSTER_SHIFT 24
 538
 539     /* Per-vCPU dynamic tracing state used to generate this TB */
 540     uint32_t trace_vcpu_dstate;
 541
 542     /*
 543      * Above fields used for comparing
 544      */
 545
 546     /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */
 547     uint16_t size;
 548     uint16_t icount;
 549
 550     struct tb_tc tc;
 551
 552     /* first and second physical page containing code. The lower bit
 553        of the pointer tells the index in page_next[].
 554        The list is protected by the TB's page('s) lock(s) */
 555     uintptr_t page_next[2];
 556     tb_page_addr_t page_addr[2];
 557
 558     /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
 559     QemuSpin jmp_lock;
 560
 561     /* The following data are used to directly call another TB from
 562      * the code of this one. This can be done either by emitting direct or
 563      * indirect native jump instructions. These jumps are reset so that the TB
 564      * just continues its execution. The TB can be linked to another one by
 565      * setting one of the jump targets (or patching the jump instruction). Only
 566      * two of such jumps are supported.
 567      */
 568     uint16_t jmp_reset_offset[2]; /* offset of original jump target */
 569 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
 570     uintptr_t jmp_target_arg[2];  /* target address or offset */
 571
 572     /*
 573      * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
 574      * Each TB can have two outgoing jumps, and therefore can participate
 575      * in two lists. The list entries are kept in jmp_list_next[2]. The least
 576      * significant bit (LSB) of the pointers in these lists is used to encode
 577      * which of the two list entries is to be used in the pointed TB.
 578      *
 579      * List traversals are protected by jmp_lock. The destination TB of each
 580      * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
 581      * can be acquired from any origin TB.
 582      *
 583      * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
 584      * being invalidated, so that no further outgoing jumps from it can be set.
 585      *
 586      * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
 587      * to a destination TB that has CF_INVALID set.
 588      */
 589     uintptr_t jmp_list_head;
 590     uintptr_t jmp_list_next[2];
 591     uintptr_t jmp_dest[2];
 592 };
 593
 594 /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
 595 static inline target_ulong tb_pc(const TranslationBlock *tb)
 596 {
 597 #if TARGET_TB_PCREL
 598     qemu_build_not_reached();
 599 #else
 600     return tb->pc;
 601 #endif
 602 }
 603
 604 /* Hide the qatomic_read to make code a little easier on the eyes */
 605 static inline uint32_t tb_cflags(const TranslationBlock *tb)
 606 {
 607     return qatomic_read(&tb->cflags);
 608 }
 609
 610 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
 611 {
 612     return tb->page_addr[0];
 613 }
 614
 615 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb)
 616 {
 617     return tb->page_addr[1];
 618 }
 619
 620 static inline void tb_set_page_addr0(TranslationBlock *tb,
 621                                      tb_page_addr_t addr)
 622 {
 623     tb->page_addr[0] = addr;
 624 }
 625
 626 static inline void tb_set_page_addr1(TranslationBlock *tb,
 627                                      tb_page_addr_t addr)
 628 {
 629     tb->page_addr[1] = addr;
 630 }
 631
 632 /* current cflags for hashing/comparison */
 633 uint32_t curr_cflags(CPUState *cpu);
 634
 635 /* TranslationBlock invalidate API */
 636 #if defined(CONFIG_USER_ONLY)
 637 void tb_invalidate_phys_addr(target_ulong addr);
 638 #else
 639 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 640 #endif
 641 void tb_flush(CPUState *cpu);
 642 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 643 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end);
 644 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
 645
 646 /* GETPC is the true target of the return instruction that we'll execute.  */
 647 #if defined(CONFIG_TCG_INTERPRETER)
 648 extern __thread uintptr_t tci_tb_ptr;
 649 # define GETPC() tci_tb_ptr
 650 #else
 651 # define GETPC() \
 652     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 653 #endif
 654
 655 /* The true return address will often point to a host insn that is part of
 656    the next translated guest insn.  Adjust the address backward to point to
 657    the middle of the call insn.  Subtracting one would do the job except for
 658    several compressed mode architectures (arm, mips) which set the low bit
 659    to indicate the compressed mode; subtracting two works around that.  It
 660    is also the case that there are no host isas that contain a call insn
 661    smaller than 4 bytes, so we don't worry about special-casing this.  */
 662 #define GETPC_ADJ   2
 663
 664 #if !defined(CONFIG_USER_ONLY)
 665
 666 /**
 667  * iotlb_to_section:
 668  * @cpu: CPU performing the access
 669  * @index: TCG CPU IOTLB entry
 670  *
 671  * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
 672  * it refers to. @index will have been initially created and returned
 673  * by memory_region_section_get_iotlb().
 674  */
 675 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
 676                                              hwaddr index, MemTxAttrs attrs);
 677 #endif
 678
 679 /**
 680  * get_page_addr_code_hostp()
 681  * @env: CPUArchState
 682  * @addr: guest virtual address of guest code
 683  *
 684  * See get_page_addr_code() (full-system version) for documentation on the
 685  * return value.
 686  *
 687  * Sets *@hostp (when @hostp is non-NULL) as follows.
 688  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
 689  * to the host address where @addr's content is kept.
 690  *
 691  * Note: this function can trigger an exception.
 692  */
 693 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
 694                                         void **hostp);
 695
 696 /**
 697  * get_page_addr_code()
 698  * @env: CPUArchState
 699  * @addr: guest virtual address of guest code
 700  *
 701  * If we cannot translate and execute from the entire RAM page, or if
 702  * the region is not backed by RAM, returns -1. Otherwise, returns the
 703  * ram_addr_t corresponding to the guest code at @addr.
 704  *
 705  * Note: this function can trigger an exception.
 706  */
 707 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
 708                                                 target_ulong addr)
 709 {
 710     return get_page_addr_code_hostp(env, addr, NULL);
 711 }
 712
 713 #if defined(CONFIG_USER_ONLY)
 714 void mmap_lock(void);
 715 void mmap_unlock(void);
 716 bool have_mmap_lock(void);
 717
 718 /**
 719  * adjust_signal_pc:
 720  * @pc: raw pc from the host signal ucontext_t.
 721  * @is_write: host memory operation was write, or read-modify-write.
 722  *
 723  * Alter @pc as required for unwinding.  Return the type of the
 724  * guest memory access -- host reads may be for guest execution.
 725  */
 726 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
 727
 728 /**
 729  * handle_sigsegv_accerr_write:
 730  * @cpu: the cpu context
 731  * @old_set: the sigset_t from the signal ucontext_t
 732  * @host_pc: the host pc, adjusted for the signal
 733  * @host_addr: the host address of the fault
 734  *
 735  * Return true if the write fault has been handled, and should be re-tried.
 736  */
 737 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
 738                                  uintptr_t host_pc, abi_ptr guest_addr);
 739
 740 /**
 741  * cpu_loop_exit_sigsegv:
 742  * @cpu: the cpu context
 743  * @addr: the guest address of the fault
 744  * @access_type: access was read/write/execute
 745  * @maperr: true for invalid page, false for permission fault
 746  * @ra: host pc for unwinding
 747  *
 748  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 749  * specific things to raise SIGSEGV, and jump to the main cpu loop.
 750  */
 751 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
 752                                       MMUAccessType access_type,
 753                                       bool maperr, uintptr_t ra);
 754
 755 /**
 756  * cpu_loop_exit_sigbus:
 757  * @cpu: the cpu context
 758  * @addr: the guest address of the alignment fault
 759  * @access_type: access was read/write/execute
 760  * @ra: host pc for unwinding
 761  *
 762  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 763  * specific things to raise SIGBUS, and jump to the main cpu loop.
 764  */
 765 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
 766                                      MMUAccessType access_type,
 767                                      uintptr_t ra);
 768
 769 #else
 770 static inline void mmap_lock(void) {}
 771 static inline void mmap_unlock(void) {}
 772
 773 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 774 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 775
 776 MemoryRegionSection *
 777 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 778                                   hwaddr *xlat, hwaddr *plen,
 779                                   MemTxAttrs attrs, int *prot);
 780 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 781                                        MemoryRegionSection *section);
 782 #endif
 783
 784 #endif