include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef EXEC_ALL_H
  21 #define EXEC_ALL_H
  22
  23 #include "cpu.h"
  24 #ifdef CONFIG_TCG
  25 #include "exec/cpu_ldst.h"
  26 #endif
  27 #include "qemu/interval-tree.h"
  28
  29 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  30 #define DEBUG_DISAS
  31
  32 /* Page tracking code uses ram addresses in system mode, and virtual
  33    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  34    type.  */
  35 #if defined(CONFIG_USER_ONLY)
  36 typedef abi_ulong tb_page_addr_t;
  37 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
  38 #else
  39 typedef ram_addr_t tb_page_addr_t;
  40 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
  41 #endif
  42
  43 /**
  44  * cpu_unwind_state_data:
  45  * @cpu: the cpu context
  46  * @host_pc: the host pc within the translation
  47  * @data: output data
  48  *
  49  * Attempt to load the the unwind state for a host pc occurring in
  50  * translated code.  If @host_pc is not in translated code, the
  51  * function returns false; otherwise @data is loaded.
  52  * This is the same unwind info as given to restore_state_to_opc.
  53  */
  54 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
  55
  56 /**
  57  * cpu_restore_state:
  58  * @cpu: the cpu context
  59  * @host_pc: the host pc within the translation
  60  * @return: true if state was restored, false otherwise
  61  *
  62  * Attempt to restore the state for a fault occurring in translated
  63  * code. If @host_pc is not in translated code no state is
  64  * restored and the function returns false.
  65  */
  66 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc);
  67
  68 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
  69 G_NORETURN void cpu_loop_exit(CPUState *cpu);
  70 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  71 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
  72
  73 /**
  74  * cpu_loop_exit_requested:
  75  * @cpu: The CPU state to be tested
  76  *
  77  * Indicate if somebody asked for a return of the CPU to the main loop
  78  * (e.g., via cpu_exit() or cpu_interrupt()).
  79  *
  80  * This is helpful for architectures that support interruptible
  81  * instructions. After writing back all state to registers/memory, this
  82  * call can be used to check if it makes sense to return to the main loop
  83  * or to continue executing the interruptible instruction.
  84  */
  85 static inline bool cpu_loop_exit_requested(CPUState *cpu)
  86 {
  87     return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0;
  88 }
  89
  90 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  91 /* cputlb.c */
  92 /**
  93  * tlb_init - initialize a CPU's TLB
  94  * @cpu: CPU whose TLB should be initialized
  95  */
  96 void tlb_init(CPUState *cpu);
  97 /**
  98  * tlb_destroy - destroy a CPU's TLB
  99  * @cpu: CPU whose TLB should be destroyed
 100  */
 101 void tlb_destroy(CPUState *cpu);
 102 /**
 103  * tlb_flush_page:
 104  * @cpu: CPU whose TLB should be flushed
 105  * @addr: virtual address of page to be flushed
 106  *
 107  * Flush one page from the TLB of the specified CPU, for all
 108  * MMU indexes.
 109  */
 110 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 111 /**
 112  * tlb_flush_page_all_cpus:
 113  * @cpu: src CPU of the flush
 114  * @addr: virtual address of page to be flushed
 115  *
 116  * Flush one page from the TLB of the specified CPU, for all
 117  * MMU indexes.
 118  */
 119 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
 120 /**
 121  * tlb_flush_page_all_cpus_synced:
 122  * @cpu: src CPU of the flush
 123  * @addr: virtual address of page to be flushed
 124  *
 125  * Flush one page from the TLB of the specified CPU, for all MMU
 126  * indexes like tlb_flush_page_all_cpus except the source vCPUs work
 127  * is scheduled as safe work meaning all flushes will be complete once
 128  * the source vCPUs safe work is complete. This will depend on when
 129  * the guests translation ends the TB.
 130  */
 131 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
 132 /**
 133  * tlb_flush:
 134  * @cpu: CPU whose TLB should be flushed
 135  *
 136  * Flush the entire TLB for the specified CPU. Most CPU architectures
 137  * allow the implementation to drop entries from the TLB at any time
 138  * so this is generally safe. If more selective flushing is required
 139  * use one of the other functions for efficiency.
 140  */
 141 void tlb_flush(CPUState *cpu);
 142 /**
 143  * tlb_flush_all_cpus:
 144  * @cpu: src CPU of the flush
 145  */
 146 void tlb_flush_all_cpus(CPUState *src_cpu);
 147 /**
 148  * tlb_flush_all_cpus_synced:
 149  * @cpu: src CPU of the flush
 150  *
 151  * Like tlb_flush_all_cpus except this except the source vCPUs work is
 152  * scheduled as safe work meaning all flushes will be complete once
 153  * the source vCPUs safe work is complete. This will depend on when
 154  * the guests translation ends the TB.
 155  */
 156 void tlb_flush_all_cpus_synced(CPUState *src_cpu);
 157 /**
 158  * tlb_flush_page_by_mmuidx:
 159  * @cpu: CPU whose TLB should be flushed
 160  * @addr: virtual address of page to be flushed
 161  * @idxmap: bitmap of MMU indexes to flush
 162  *
 163  * Flush one page from the TLB of the specified CPU, for the specified
 164  * MMU indexes.
 165  */
 166 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
 167                               uint16_t idxmap);
 168 /**
 169  * tlb_flush_page_by_mmuidx_all_cpus:
 170  * @cpu: Originating CPU of the flush
 171  * @addr: virtual address of page to be flushed
 172  * @idxmap: bitmap of MMU indexes to flush
 173  *
 174  * Flush one page from the TLB of all CPUs, for the specified
 175  * MMU indexes.
 176  */
 177 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 178                                        uint16_t idxmap);
 179 /**
 180  * tlb_flush_page_by_mmuidx_all_cpus_synced:
 181  * @cpu: Originating CPU of the flush
 182  * @addr: virtual address of page to be flushed
 183  * @idxmap: bitmap of MMU indexes to flush
 184  *
 185  * Flush one page from the TLB of all CPUs, for the specified MMU
 186  * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
 187  * vCPUs work is scheduled as safe work meaning all flushes will be
 188  * complete once  the source vCPUs safe work is complete. This will
 189  * depend on when the guests translation ends the TB.
 190  */
 191 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 192                                               uint16_t idxmap);
 193 /**
 194  * tlb_flush_by_mmuidx:
 195  * @cpu: CPU whose TLB should be flushed
 196  * @wait: If true ensure synchronisation by exiting the cpu_loop
 197  * @idxmap: bitmap of MMU indexes to flush
 198  *
 199  * Flush all entries from the TLB of the specified CPU, for the specified
 200  * MMU indexes.
 201  */
 202 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
 203 /**
 204  * tlb_flush_by_mmuidx_all_cpus:
 205  * @cpu: Originating CPU of the flush
 206  * @idxmap: bitmap of MMU indexes to flush
 207  *
 208  * Flush all entries from all TLBs of all CPUs, for the specified
 209  * MMU indexes.
 210  */
 211 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
 212 /**
 213  * tlb_flush_by_mmuidx_all_cpus_synced:
 214  * @cpu: Originating CPU of the flush
 215  * @idxmap: bitmap of MMU indexes to flush
 216  *
 217  * Flush all entries from all TLBs of all CPUs, for the specified
 218  * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
 219  * vCPUs work is scheduled as safe work meaning all flushes will be
 220  * complete once  the source vCPUs safe work is complete. This will
 221  * depend on when the guests translation ends the TB.
 222  */
 223 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
 224
 225 /**
 226  * tlb_flush_page_bits_by_mmuidx
 227  * @cpu: CPU whose TLB should be flushed
 228  * @addr: virtual address of page to be flushed
 229  * @idxmap: bitmap of mmu indexes to flush
 230  * @bits: number of significant bits in address
 231  *
 232  * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
 233  */
 234 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
 235                                    uint16_t idxmap, unsigned bits);
 236
 237 /* Similarly, with broadcast and syncing. */
 238 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 239                                             uint16_t idxmap, unsigned bits);
 240 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
 241     (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
 242
 243 /**
 244  * tlb_flush_range_by_mmuidx
 245  * @cpu: CPU whose TLB should be flushed
 246  * @addr: virtual address of the start of the range to be flushed
 247  * @len: length of range to be flushed
 248  * @idxmap: bitmap of mmu indexes to flush
 249  * @bits: number of significant bits in address
 250  *
 251  * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
 252  * comparing only the low @bits worth of each virtual page.
 253  */
 254 void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 255                                target_ulong len, uint16_t idxmap,
 256                                unsigned bits);
 257
 258 /* Similarly, with broadcast and syncing. */
 259 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 260                                         target_ulong len, uint16_t idxmap,
 261                                         unsigned bits);
 262 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 263                                                target_ulong addr,
 264                                                target_ulong len,
 265                                                uint16_t idxmap,
 266                                                unsigned bits);
 267
 268 /**
 269  * tlb_set_page_full:
 270  * @cpu: CPU context
 271  * @mmu_idx: mmu index of the tlb to modify
 272  * @vaddr: virtual address of the entry to add
 273  * @full: the details of the tlb entry
 274  *
 275  * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
 276  * @full must be filled, except for xlat_section, and constitute
 277  * the complete description of the translated page.
 278  *
 279  * This is generally called by the target tlb_fill function after
 280  * having performed a successful page table walk to find the physical
 281  * address and attributes for the translation.
 282  *
 283  * At most one entry for a given virtual address is permitted. Only a
 284  * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
 285  * used by tlb_flush_page.
 286  */
 287 void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
 288                        CPUTLBEntryFull *full);
 289
 290 /**
 291  * tlb_set_page_with_attrs:
 292  * @cpu: CPU to add this TLB entry for
 293  * @vaddr: virtual address of page to add entry for
 294  * @paddr: physical address of the page
 295  * @attrs: memory transaction attributes
 296  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 297  * @mmu_idx: MMU index to insert TLB entry for
 298  * @size: size of the page in bytes
 299  *
 300  * Add an entry to this CPU's TLB (a mapping from virtual address
 301  * @vaddr to physical address @paddr) with the specified memory
 302  * transaction attributes. This is generally called by the target CPU
 303  * specific code after it has been called through the tlb_fill()
 304  * entry point and performed a successful page table walk to find
 305  * the physical address and attributes for the virtual address
 306  * which provoked the TLB miss.
 307  *
 308  * At most one entry for a given virtual address is permitted. Only a
 309  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 310  * used by tlb_flush_page.
 311  */
 312 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 313                              hwaddr paddr, MemTxAttrs attrs,
 314                              int prot, int mmu_idx, target_ulong size);
 315 /* tlb_set_page:
 316  *
 317  * This function is equivalent to calling tlb_set_page_with_attrs()
 318  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 319  * as a convenience for CPUs which don't use memory transaction attributes.
 320  */
 321 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 322                   hwaddr paddr, int prot,
 323                   int mmu_idx, target_ulong size);
 324 #else
 325 static inline void tlb_init(CPUState *cpu)
 326 {
 327 }
 328 static inline void tlb_destroy(CPUState *cpu)
 329 {
 330 }
 331 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 332 {
 333 }
 334 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
 335 {
 336 }
 337 static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
 338                                                   target_ulong addr)
 339 {
 340 }
 341 static inline void tlb_flush(CPUState *cpu)
 342 {
 343 }
 344 static inline void tlb_flush_all_cpus(CPUState *src_cpu)
 345 {
 346 }
 347 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
 348 {
 349 }
 350 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 351                                             target_ulong addr, uint16_t idxmap)
 352 {
 353 }
 354
 355 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
 356 {
 357 }
 358 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
 359                                                      target_ulong addr,
 360                                                      uint16_t idxmap)
 361 {
 362 }
 363 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
 364                                                             target_ulong addr,
 365                                                             uint16_t idxmap)
 366 {
 367 }
 368 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
 369 {
 370 }
 371
 372 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
 373                                                        uint16_t idxmap)
 374 {
 375 }
 376 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
 377                                                  target_ulong addr,
 378                                                  uint16_t idxmap,
 379                                                  unsigned bits)
 380 {
 381 }
 382 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
 383                                                           target_ulong addr,
 384                                                           uint16_t idxmap,
 385                                                           unsigned bits)
 386 {
 387 }
 388 static inline void
 389 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 390                                               uint16_t idxmap, unsigned bits)
 391 {
 392 }
 393 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 394                                              target_ulong len, uint16_t idxmap,
 395                                              unsigned bits)
 396 {
 397 }
 398 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
 399                                                       target_ulong addr,
 400                                                       target_ulong len,
 401                                                       uint16_t idxmap,
 402                                                       unsigned bits)
 403 {
 404 }
 405 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 406                                                              target_ulong addr,
 407                                                              target_long len,
 408                                                              uint16_t idxmap,
 409                                                              unsigned bits)
 410 {
 411 }
 412 #endif
 413 /**
 414  * probe_access:
 415  * @env: CPUArchState
 416  * @addr: guest virtual address to look up
 417  * @size: size of the access
 418  * @access_type: read, write or execute permission
 419  * @mmu_idx: MMU index to use for lookup
 420  * @retaddr: return address for unwinding
 421  *
 422  * Look up the guest virtual address @addr.  Raise an exception if the
 423  * page does not satisfy @access_type.  Raise an exception if the
 424  * access (@addr, @size) hits a watchpoint.  For writes, mark a clean
 425  * page as dirty.
 426  *
 427  * Finally, return the host address for a page that is backed by RAM,
 428  * or NULL if the page requires I/O.
 429  */
 430 void *probe_access(CPUArchState *env, target_ulong addr, int size,
 431                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 432
 433 static inline void *probe_write(CPUArchState *env, target_ulong addr, int size,
 434                                 int mmu_idx, uintptr_t retaddr)
 435 {
 436     return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
 437 }
 438
 439 static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
 440                                int mmu_idx, uintptr_t retaddr)
 441 {
 442     return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
 443 }
 444
 445 /**
 446  * probe_access_flags:
 447  * @env: CPUArchState
 448  * @addr: guest virtual address to look up
 449  * @access_type: read, write or execute permission
 450  * @mmu_idx: MMU index to use for lookup
 451  * @nonfault: suppress the fault
 452  * @phost: return value for host address
 453  * @retaddr: return address for unwinding
 454  *
 455  * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
 456  * the page, and storing the host address for RAM in @phost.
 457  *
 458  * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
 459  * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
 460  * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
 461  * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
 462  */
 463 int probe_access_flags(CPUArchState *env, target_ulong addr,
 464                        MMUAccessType access_type, int mmu_idx,
 465                        bool nonfault, void **phost, uintptr_t retaddr);
 466
 467 #ifndef CONFIG_USER_ONLY
 468 /**
 469  * probe_access_full:
 470  * Like probe_access_flags, except also return into @pfull.
 471  *
 472  * The CPUTLBEntryFull structure returned via @pfull is transient
 473  * and must be consumed or copied immediately, before any further
 474  * access or changes to TLB @mmu_idx.
 475  */
 476 int probe_access_full(CPUArchState *env, target_ulong addr,
 477                       MMUAccessType access_type, int mmu_idx,
 478                       bool nonfault, void **phost,
 479                       CPUTLBEntryFull **pfull, uintptr_t retaddr);
 480 #endif
 481
 482 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 483
 484 /* Estimated block size for TB allocation.  */
 485 /* ??? The following is based on a 2015 survey of x86_64 host output.
 486    Better would seem to be some sort of dynamically sized TB array,
 487    adapting to the block sizes actually being produced.  */
 488 #if defined(CONFIG_SOFTMMU)
 489 #define CODE_GEN_AVG_BLOCK_SIZE 400
 490 #else
 491 #define CODE_GEN_AVG_BLOCK_SIZE 150
 492 #endif
 493
 494 /*
 495  * Translation Cache-related fields of a TB.
 496  * This struct exists just for convenience; we keep track of TB's in a binary
 497  * search tree, and the only fields needed to compare TB's in the tree are
 498  * @ptr and @size.
 499  * Note: the address of search data can be obtained by adding @size to @ptr.
 500  */
 501 struct tb_tc {
 502     const void *ptr;    /* pointer to the translated code */
 503     size_t size;
 504 };
 505
 506 struct TranslationBlock {
 507 #if !TARGET_TB_PCREL
 508     /*
 509      * Guest PC corresponding to this block.  This must be the true
 510      * virtual address.  Therefore e.g. x86 stores EIP + CS_BASE, and
 511      * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
 512      * privilege, must store those bits elsewhere.
 513      *
 514      * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
 515      * written such that the TB is associated only with the physical
 516      * page and may be run in any virtual address context.  In this case,
 517      * PC must always be taken from ENV in a target-specific manner.
 518      * Unwind information is taken as offsets from the page, to be
 519      * deposited into the "current" PC.
 520      */
 521     target_ulong pc;
 522 #endif
 523
 524     /*
 525      * Target-specific data associated with the TranslationBlock, e.g.:
 526      * x86: the original user, the Code Segment virtual base,
 527      * arm: an extension of tb->flags,
 528      * s390x: instruction data for EXECUTE,
 529      * sparc: the next pc of the instruction queue (for delay slots).
 530      */
 531     target_ulong cs_base;
 532
 533     uint32_t flags; /* flags defining in which context the code was generated */
 534     uint32_t cflags;    /* compile flags */
 535
 536 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */
 537 #define CF_COUNT_MASK    0x000001ff
 538 #define CF_NO_GOTO_TB    0x00000200 /* Do not chain with goto_tb */
 539 #define CF_NO_GOTO_PTR   0x00000400 /* Do not chain with goto_ptr */
 540 #define CF_SINGLE_STEP   0x00000800 /* gdbstub single-step in effect */
 541 #define CF_LAST_IO       0x00008000 /* Last insn may be an IO access.  */
 542 #define CF_MEMI_ONLY     0x00010000 /* Only instrument memory ops */
 543 #define CF_USE_ICOUNT    0x00020000
 544 #define CF_INVALID       0x00040000 /* TB is stale. Set with @jmp_lock held */
 545 #define CF_PARALLEL      0x00080000 /* Generate code for a parallel context */
 546 #define CF_NOIRQ         0x00100000 /* Generate an uninterruptible TB */
 547 #define CF_CLUSTER_MASK  0xff000000 /* Top 8 bits are cluster ID */
 548 #define CF_CLUSTER_SHIFT 24
 549
 550     /* Per-vCPU dynamic tracing state used to generate this TB */
 551     uint32_t trace_vcpu_dstate;
 552
 553     /*
 554      * Above fields used for comparing
 555      */
 556
 557     /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */
 558     uint16_t size;
 559     uint16_t icount;
 560
 561     struct tb_tc tc;
 562
 563     /*
 564      * Track tb_page_addr_t intervals that intersect this TB.
 565      * For user-only, the virtual addresses are always contiguous,
 566      * and we use a unified interval tree.  For system, we use a
 567      * linked list headed in each PageDesc.  Within the list, the lsb
 568      * of the previous pointer tells the index of page_next[], and the
 569      * list is protected by the PageDesc lock(s).
 570      */
 571 #ifdef CONFIG_USER_ONLY
 572     IntervalTreeNode itree;
 573 #else
 574     uintptr_t page_next[2];
 575     tb_page_addr_t page_addr[2];
 576 #endif
 577
 578     /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
 579     QemuSpin jmp_lock;
 580
 581     /* The following data are used to directly call another TB from
 582      * the code of this one. This can be done either by emitting direct or
 583      * indirect native jump instructions. These jumps are reset so that the TB
 584      * just continues its execution. The TB can be linked to another one by
 585      * setting one of the jump targets (or patching the jump instruction). Only
 586      * two of such jumps are supported.
 587      */
 588     uint16_t jmp_reset_offset[2]; /* offset of original jump target */
 589 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
 590     uintptr_t jmp_target_arg[2];  /* target address or offset */
 591
 592     /*
 593      * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
 594      * Each TB can have two outgoing jumps, and therefore can participate
 595      * in two lists. The list entries are kept in jmp_list_next[2]. The least
 596      * significant bit (LSB) of the pointers in these lists is used to encode
 597      * which of the two list entries is to be used in the pointed TB.
 598      *
 599      * List traversals are protected by jmp_lock. The destination TB of each
 600      * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
 601      * can be acquired from any origin TB.
 602      *
 603      * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
 604      * being invalidated, so that no further outgoing jumps from it can be set.
 605      *
 606      * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
 607      * to a destination TB that has CF_INVALID set.
 608      */
 609     uintptr_t jmp_list_head;
 610     uintptr_t jmp_list_next[2];
 611     uintptr_t jmp_dest[2];
 612 };
 613
 614 /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
 615 static inline target_ulong tb_pc(const TranslationBlock *tb)
 616 {
 617 #if TARGET_TB_PCREL
 618     qemu_build_not_reached();
 619 #else
 620     return tb->pc;
 621 #endif
 622 }
 623
 624 /* Hide the qatomic_read to make code a little easier on the eyes */
 625 static inline uint32_t tb_cflags(const TranslationBlock *tb)
 626 {
 627     return qatomic_read(&tb->cflags);
 628 }
 629
 630 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
 631 {
 632 #ifdef CONFIG_USER_ONLY
 633     return tb->itree.start;
 634 #else
 635     return tb->page_addr[0];
 636 #endif
 637 }
 638
 639 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb)
 640 {
 641 #ifdef CONFIG_USER_ONLY
 642     tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK;
 643     return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next;
 644 #else
 645     return tb->page_addr[1];
 646 #endif
 647 }
 648
 649 static inline void tb_set_page_addr0(TranslationBlock *tb,
 650                                      tb_page_addr_t addr)
 651 {
 652 #ifdef CONFIG_USER_ONLY
 653     tb->itree.start = addr;
 654     /*
 655      * To begin, we record an interval of one byte.  When the translation
 656      * loop encounters a second page, the interval will be extended to
 657      * include the first byte of the second page, which is sufficient to
 658      * allow tb_page_addr1() above to work properly.  The final corrected
 659      * interval will be set by tb_page_add() from tb->size before the
 660      * node is added to the interval tree.
 661      */
 662     tb->itree.last = addr;
 663 #else
 664     tb->page_addr[0] = addr;
 665 #endif
 666 }
 667
 668 static inline void tb_set_page_addr1(TranslationBlock *tb,
 669                                      tb_page_addr_t addr)
 670 {
 671 #ifdef CONFIG_USER_ONLY
 672     /* Extend the interval to the first byte of the second page.  See above. */
 673     tb->itree.last = addr;
 674 #else
 675     tb->page_addr[1] = addr;
 676 #endif
 677 }
 678
 679 /* current cflags for hashing/comparison */
 680 uint32_t curr_cflags(CPUState *cpu);
 681
 682 /* TranslationBlock invalidate API */
 683 #if defined(CONFIG_USER_ONLY)
 684 void tb_invalidate_phys_addr(target_ulong addr);
 685 #else
 686 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 687 #endif
 688 void tb_flush(CPUState *cpu);
 689 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 690 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end);
 691 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
 692
 693 /* GETPC is the true target of the return instruction that we'll execute.  */
 694 #if defined(CONFIG_TCG_INTERPRETER)
 695 extern __thread uintptr_t tci_tb_ptr;
 696 # define GETPC() tci_tb_ptr
 697 #else
 698 # define GETPC() \
 699     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 700 #endif
 701
 702 /* The true return address will often point to a host insn that is part of
 703    the next translated guest insn.  Adjust the address backward to point to
 704    the middle of the call insn.  Subtracting one would do the job except for
 705    several compressed mode architectures (arm, mips) which set the low bit
 706    to indicate the compressed mode; subtracting two works around that.  It
 707    is also the case that there are no host isas that contain a call insn
 708    smaller than 4 bytes, so we don't worry about special-casing this.  */
 709 #define GETPC_ADJ   2
 710
 711 #if !defined(CONFIG_USER_ONLY)
 712
 713 /**
 714  * iotlb_to_section:
 715  * @cpu: CPU performing the access
 716  * @index: TCG CPU IOTLB entry
 717  *
 718  * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
 719  * it refers to. @index will have been initially created and returned
 720  * by memory_region_section_get_iotlb().
 721  */
 722 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
 723                                              hwaddr index, MemTxAttrs attrs);
 724 #endif
 725
 726 /**
 727  * get_page_addr_code_hostp()
 728  * @env: CPUArchState
 729  * @addr: guest virtual address of guest code
 730  *
 731  * See get_page_addr_code() (full-system version) for documentation on the
 732  * return value.
 733  *
 734  * Sets *@hostp (when @hostp is non-NULL) as follows.
 735  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
 736  * to the host address where @addr's content is kept.
 737  *
 738  * Note: this function can trigger an exception.
 739  */
 740 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
 741                                         void **hostp);
 742
 743 /**
 744  * get_page_addr_code()
 745  * @env: CPUArchState
 746  * @addr: guest virtual address of guest code
 747  *
 748  * If we cannot translate and execute from the entire RAM page, or if
 749  * the region is not backed by RAM, returns -1. Otherwise, returns the
 750  * ram_addr_t corresponding to the guest code at @addr.
 751  *
 752  * Note: this function can trigger an exception.
 753  */
 754 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
 755                                                 target_ulong addr)
 756 {
 757     return get_page_addr_code_hostp(env, addr, NULL);
 758 }
 759
 760 #if defined(CONFIG_USER_ONLY)
 761 void mmap_lock(void);
 762 void mmap_unlock(void);
 763 bool have_mmap_lock(void);
 764
 765 /**
 766  * adjust_signal_pc:
 767  * @pc: raw pc from the host signal ucontext_t.
 768  * @is_write: host memory operation was write, or read-modify-write.
 769  *
 770  * Alter @pc as required for unwinding.  Return the type of the
 771  * guest memory access -- host reads may be for guest execution.
 772  */
 773 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
 774
 775 /**
 776  * handle_sigsegv_accerr_write:
 777  * @cpu: the cpu context
 778  * @old_set: the sigset_t from the signal ucontext_t
 779  * @host_pc: the host pc, adjusted for the signal
 780  * @host_addr: the host address of the fault
 781  *
 782  * Return true if the write fault has been handled, and should be re-tried.
 783  */
 784 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
 785                                  uintptr_t host_pc, abi_ptr guest_addr);
 786
 787 /**
 788  * cpu_loop_exit_sigsegv:
 789  * @cpu: the cpu context
 790  * @addr: the guest address of the fault
 791  * @access_type: access was read/write/execute
 792  * @maperr: true for invalid page, false for permission fault
 793  * @ra: host pc for unwinding
 794  *
 795  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 796  * specific things to raise SIGSEGV, and jump to the main cpu loop.
 797  */
 798 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
 799                                       MMUAccessType access_type,
 800                                       bool maperr, uintptr_t ra);
 801
 802 /**
 803  * cpu_loop_exit_sigbus:
 804  * @cpu: the cpu context
 805  * @addr: the guest address of the alignment fault
 806  * @access_type: access was read/write/execute
 807  * @ra: host pc for unwinding
 808  *
 809  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 810  * specific things to raise SIGBUS, and jump to the main cpu loop.
 811  */
 812 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
 813                                      MMUAccessType access_type,
 814                                      uintptr_t ra);
 815
 816 #else
 817 static inline void mmap_lock(void) {}
 818 static inline void mmap_unlock(void) {}
 819
 820 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 821 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 822
 823 MemoryRegionSection *
 824 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 825                                   hwaddr *xlat, hwaddr *plen,
 826                                   MemTxAttrs attrs, int *prot);
 827 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 828                                        MemoryRegionSection *section);
 829 #endif
 830
 831 #endif