include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef EXEC_ALL_H
  21 #define EXEC_ALL_H
  22
  23 #include "cpu.h"
  24 #ifdef CONFIG_TCG
  25 #include "exec/cpu_ldst.h"
  26 #endif
  27 #include "qemu/interval-tree.h"
  28 #include "qemu/clang-tsa.h"
  29
  30 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  31 #define DEBUG_DISAS
  32
  33 /* Page tracking code uses ram addresses in system mode, and virtual
  34    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  35    type.  */
  36 #if defined(CONFIG_USER_ONLY)
  37 typedef abi_ulong tb_page_addr_t;
  38 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
  39 #else
  40 typedef ram_addr_t tb_page_addr_t;
  41 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
  42 #endif
  43
  44 /**
  45  * cpu_unwind_state_data:
  46  * @cpu: the cpu context
  47  * @host_pc: the host pc within the translation
  48  * @data: output data
  49  *
  50  * Attempt to load the the unwind state for a host pc occurring in
  51  * translated code.  If @host_pc is not in translated code, the
  52  * function returns false; otherwise @data is loaded.
  53  * This is the same unwind info as given to restore_state_to_opc.
  54  */
  55 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
  56
  57 /**
  58  * cpu_restore_state:
  59  * @cpu: the cpu context
  60  * @host_pc: the host pc within the translation
  61  * @return: true if state was restored, false otherwise
  62  *
  63  * Attempt to restore the state for a fault occurring in translated
  64  * code. If @host_pc is not in translated code no state is
  65  * restored and the function returns false.
  66  */
  67 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc);
  68
  69 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
  70 G_NORETURN void cpu_loop_exit(CPUState *cpu);
  71 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  72 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
  73
  74 /**
  75  * cpu_loop_exit_requested:
  76  * @cpu: The CPU state to be tested
  77  *
  78  * Indicate if somebody asked for a return of the CPU to the main loop
  79  * (e.g., via cpu_exit() or cpu_interrupt()).
  80  *
  81  * This is helpful for architectures that support interruptible
  82  * instructions. After writing back all state to registers/memory, this
  83  * call can be used to check if it makes sense to return to the main loop
  84  * or to continue executing the interruptible instruction.
  85  */
  86 static inline bool cpu_loop_exit_requested(CPUState *cpu)
  87 {
  88     return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0;
  89 }
  90
  91 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  92 /* cputlb.c */
  93 /**
  94  * tlb_init - initialize a CPU's TLB
  95  * @cpu: CPU whose TLB should be initialized
  96  */
  97 void tlb_init(CPUState *cpu);
  98 /**
  99  * tlb_destroy - destroy a CPU's TLB
 100  * @cpu: CPU whose TLB should be destroyed
 101  */
 102 void tlb_destroy(CPUState *cpu);
 103 /**
 104  * tlb_flush_page:
 105  * @cpu: CPU whose TLB should be flushed
 106  * @addr: virtual address of page to be flushed
 107  *
 108  * Flush one page from the TLB of the specified CPU, for all
 109  * MMU indexes.
 110  */
 111 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 112 /**
 113  * tlb_flush_page_all_cpus:
 114  * @cpu: src CPU of the flush
 115  * @addr: virtual address of page to be flushed
 116  *
 117  * Flush one page from the TLB of the specified CPU, for all
 118  * MMU indexes.
 119  */
 120 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
 121 /**
 122  * tlb_flush_page_all_cpus_synced:
 123  * @cpu: src CPU of the flush
 124  * @addr: virtual address of page to be flushed
 125  *
 126  * Flush one page from the TLB of the specified CPU, for all MMU
 127  * indexes like tlb_flush_page_all_cpus except the source vCPUs work
 128  * is scheduled as safe work meaning all flushes will be complete once
 129  * the source vCPUs safe work is complete. This will depend on when
 130  * the guests translation ends the TB.
 131  */
 132 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
 133 /**
 134  * tlb_flush:
 135  * @cpu: CPU whose TLB should be flushed
 136  *
 137  * Flush the entire TLB for the specified CPU. Most CPU architectures
 138  * allow the implementation to drop entries from the TLB at any time
 139  * so this is generally safe. If more selective flushing is required
 140  * use one of the other functions for efficiency.
 141  */
 142 void tlb_flush(CPUState *cpu);
 143 /**
 144  * tlb_flush_all_cpus:
 145  * @cpu: src CPU of the flush
 146  */
 147 void tlb_flush_all_cpus(CPUState *src_cpu);
 148 /**
 149  * tlb_flush_all_cpus_synced:
 150  * @cpu: src CPU of the flush
 151  *
 152  * Like tlb_flush_all_cpus except this except the source vCPUs work is
 153  * scheduled as safe work meaning all flushes will be complete once
 154  * the source vCPUs safe work is complete. This will depend on when
 155  * the guests translation ends the TB.
 156  */
 157 void tlb_flush_all_cpus_synced(CPUState *src_cpu);
 158 /**
 159  * tlb_flush_page_by_mmuidx:
 160  * @cpu: CPU whose TLB should be flushed
 161  * @addr: virtual address of page to be flushed
 162  * @idxmap: bitmap of MMU indexes to flush
 163  *
 164  * Flush one page from the TLB of the specified CPU, for the specified
 165  * MMU indexes.
 166  */
 167 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
 168                               uint16_t idxmap);
 169 /**
 170  * tlb_flush_page_by_mmuidx_all_cpus:
 171  * @cpu: Originating CPU of the flush
 172  * @addr: virtual address of page to be flushed
 173  * @idxmap: bitmap of MMU indexes to flush
 174  *
 175  * Flush one page from the TLB of all CPUs, for the specified
 176  * MMU indexes.
 177  */
 178 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 179                                        uint16_t idxmap);
 180 /**
 181  * tlb_flush_page_by_mmuidx_all_cpus_synced:
 182  * @cpu: Originating CPU of the flush
 183  * @addr: virtual address of page to be flushed
 184  * @idxmap: bitmap of MMU indexes to flush
 185  *
 186  * Flush one page from the TLB of all CPUs, for the specified MMU
 187  * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
 188  * vCPUs work is scheduled as safe work meaning all flushes will be
 189  * complete once  the source vCPUs safe work is complete. This will
 190  * depend on when the guests translation ends the TB.
 191  */
 192 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 193                                               uint16_t idxmap);
 194 /**
 195  * tlb_flush_by_mmuidx:
 196  * @cpu: CPU whose TLB should be flushed
 197  * @wait: If true ensure synchronisation by exiting the cpu_loop
 198  * @idxmap: bitmap of MMU indexes to flush
 199  *
 200  * Flush all entries from the TLB of the specified CPU, for the specified
 201  * MMU indexes.
 202  */
 203 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
 204 /**
 205  * tlb_flush_by_mmuidx_all_cpus:
 206  * @cpu: Originating CPU of the flush
 207  * @idxmap: bitmap of MMU indexes to flush
 208  *
 209  * Flush all entries from all TLBs of all CPUs, for the specified
 210  * MMU indexes.
 211  */
 212 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
 213 /**
 214  * tlb_flush_by_mmuidx_all_cpus_synced:
 215  * @cpu: Originating CPU of the flush
 216  * @idxmap: bitmap of MMU indexes to flush
 217  *
 218  * Flush all entries from all TLBs of all CPUs, for the specified
 219  * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
 220  * vCPUs work is scheduled as safe work meaning all flushes will be
 221  * complete once  the source vCPUs safe work is complete. This will
 222  * depend on when the guests translation ends the TB.
 223  */
 224 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
 225
 226 /**
 227  * tlb_flush_page_bits_by_mmuidx
 228  * @cpu: CPU whose TLB should be flushed
 229  * @addr: virtual address of page to be flushed
 230  * @idxmap: bitmap of mmu indexes to flush
 231  * @bits: number of significant bits in address
 232  *
 233  * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
 234  */
 235 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
 236                                    uint16_t idxmap, unsigned bits);
 237
 238 /* Similarly, with broadcast and syncing. */
 239 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 240                                             uint16_t idxmap, unsigned bits);
 241 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
 242     (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
 243
 244 /**
 245  * tlb_flush_range_by_mmuidx
 246  * @cpu: CPU whose TLB should be flushed
 247  * @addr: virtual address of the start of the range to be flushed
 248  * @len: length of range to be flushed
 249  * @idxmap: bitmap of mmu indexes to flush
 250  * @bits: number of significant bits in address
 251  *
 252  * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
 253  * comparing only the low @bits worth of each virtual page.
 254  */
 255 void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 256                                target_ulong len, uint16_t idxmap,
 257                                unsigned bits);
 258
 259 /* Similarly, with broadcast and syncing. */
 260 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 261                                         target_ulong len, uint16_t idxmap,
 262                                         unsigned bits);
 263 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 264                                                target_ulong addr,
 265                                                target_ulong len,
 266                                                uint16_t idxmap,
 267                                                unsigned bits);
 268
 269 /**
 270  * tlb_set_page_full:
 271  * @cpu: CPU context
 272  * @mmu_idx: mmu index of the tlb to modify
 273  * @vaddr: virtual address of the entry to add
 274  * @full: the details of the tlb entry
 275  *
 276  * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
 277  * @full must be filled, except for xlat_section, and constitute
 278  * the complete description of the translated page.
 279  *
 280  * This is generally called by the target tlb_fill function after
 281  * having performed a successful page table walk to find the physical
 282  * address and attributes for the translation.
 283  *
 284  * At most one entry for a given virtual address is permitted. Only a
 285  * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
 286  * used by tlb_flush_page.
 287  */
 288 void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
 289                        CPUTLBEntryFull *full);
 290
 291 /**
 292  * tlb_set_page_with_attrs:
 293  * @cpu: CPU to add this TLB entry for
 294  * @vaddr: virtual address of page to add entry for
 295  * @paddr: physical address of the page
 296  * @attrs: memory transaction attributes
 297  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 298  * @mmu_idx: MMU index to insert TLB entry for
 299  * @size: size of the page in bytes
 300  *
 301  * Add an entry to this CPU's TLB (a mapping from virtual address
 302  * @vaddr to physical address @paddr) with the specified memory
 303  * transaction attributes. This is generally called by the target CPU
 304  * specific code after it has been called through the tlb_fill()
 305  * entry point and performed a successful page table walk to find
 306  * the physical address and attributes for the virtual address
 307  * which provoked the TLB miss.
 308  *
 309  * At most one entry for a given virtual address is permitted. Only a
 310  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 311  * used by tlb_flush_page.
 312  */
 313 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 314                              hwaddr paddr, MemTxAttrs attrs,
 315                              int prot, int mmu_idx, target_ulong size);
 316 /* tlb_set_page:
 317  *
 318  * This function is equivalent to calling tlb_set_page_with_attrs()
 319  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 320  * as a convenience for CPUs which don't use memory transaction attributes.
 321  */
 322 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 323                   hwaddr paddr, int prot,
 324                   int mmu_idx, target_ulong size);
 325 #else
 326 static inline void tlb_init(CPUState *cpu)
 327 {
 328 }
 329 static inline void tlb_destroy(CPUState *cpu)
 330 {
 331 }
 332 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 333 {
 334 }
 335 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
 336 {
 337 }
 338 static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
 339                                                   target_ulong addr)
 340 {
 341 }
 342 static inline void tlb_flush(CPUState *cpu)
 343 {
 344 }
 345 static inline void tlb_flush_all_cpus(CPUState *src_cpu)
 346 {
 347 }
 348 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
 349 {
 350 }
 351 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 352                                             target_ulong addr, uint16_t idxmap)
 353 {
 354 }
 355
 356 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
 357 {
 358 }
 359 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
 360                                                      target_ulong addr,
 361                                                      uint16_t idxmap)
 362 {
 363 }
 364 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
 365                                                             target_ulong addr,
 366                                                             uint16_t idxmap)
 367 {
 368 }
 369 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
 370 {
 371 }
 372
 373 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
 374                                                        uint16_t idxmap)
 375 {
 376 }
 377 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
 378                                                  target_ulong addr,
 379                                                  uint16_t idxmap,
 380                                                  unsigned bits)
 381 {
 382 }
 383 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
 384                                                           target_ulong addr,
 385                                                           uint16_t idxmap,
 386                                                           unsigned bits)
 387 {
 388 }
 389 static inline void
 390 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 391                                               uint16_t idxmap, unsigned bits)
 392 {
 393 }
 394 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 395                                              target_ulong len, uint16_t idxmap,
 396                                              unsigned bits)
 397 {
 398 }
 399 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
 400                                                       target_ulong addr,
 401                                                       target_ulong len,
 402                                                       uint16_t idxmap,
 403                                                       unsigned bits)
 404 {
 405 }
 406 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 407                                                              target_ulong addr,
 408                                                              target_long len,
 409                                                              uint16_t idxmap,
 410                                                              unsigned bits)
 411 {
 412 }
 413 #endif
 414 /**
 415  * probe_access:
 416  * @env: CPUArchState
 417  * @addr: guest virtual address to look up
 418  * @size: size of the access
 419  * @access_type: read, write or execute permission
 420  * @mmu_idx: MMU index to use for lookup
 421  * @retaddr: return address for unwinding
 422  *
 423  * Look up the guest virtual address @addr.  Raise an exception if the
 424  * page does not satisfy @access_type.  Raise an exception if the
 425  * access (@addr, @size) hits a watchpoint.  For writes, mark a clean
 426  * page as dirty.
 427  *
 428  * Finally, return the host address for a page that is backed by RAM,
 429  * or NULL if the page requires I/O.
 430  */
 431 void *probe_access(CPUArchState *env, target_ulong addr, int size,
 432                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 433
 434 static inline void *probe_write(CPUArchState *env, target_ulong addr, int size,
 435                                 int mmu_idx, uintptr_t retaddr)
 436 {
 437     return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
 438 }
 439
 440 static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
 441                                int mmu_idx, uintptr_t retaddr)
 442 {
 443     return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
 444 }
 445
 446 /**
 447  * probe_access_flags:
 448  * @env: CPUArchState
 449  * @addr: guest virtual address to look up
 450  * @size: size of the access
 451  * @access_type: read, write or execute permission
 452  * @mmu_idx: MMU index to use for lookup
 453  * @nonfault: suppress the fault
 454  * @phost: return value for host address
 455  * @retaddr: return address for unwinding
 456  *
 457  * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
 458  * the page, and storing the host address for RAM in @phost.
 459  *
 460  * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
 461  * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
 462  * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
 463  * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
 464  */
 465 int probe_access_flags(CPUArchState *env, target_ulong addr, int size,
 466                        MMUAccessType access_type, int mmu_idx,
 467                        bool nonfault, void **phost, uintptr_t retaddr);
 468
 469 #ifndef CONFIG_USER_ONLY
 470 /**
 471  * probe_access_full:
 472  * Like probe_access_flags, except also return into @pfull.
 473  *
 474  * The CPUTLBEntryFull structure returned via @pfull is transient
 475  * and must be consumed or copied immediately, before any further
 476  * access or changes to TLB @mmu_idx.
 477  */
 478 int probe_access_full(CPUArchState *env, target_ulong addr,
 479                       MMUAccessType access_type, int mmu_idx,
 480                       bool nonfault, void **phost,
 481                       CPUTLBEntryFull **pfull, uintptr_t retaddr);
 482 #endif
 483
 484 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 485
 486 /* Estimated block size for TB allocation.  */
 487 /* ??? The following is based on a 2015 survey of x86_64 host output.
 488    Better would seem to be some sort of dynamically sized TB array,
 489    adapting to the block sizes actually being produced.  */
 490 #if defined(CONFIG_SOFTMMU)
 491 #define CODE_GEN_AVG_BLOCK_SIZE 400
 492 #else
 493 #define CODE_GEN_AVG_BLOCK_SIZE 150
 494 #endif
 495
 496 /*
 497  * Translation Cache-related fields of a TB.
 498  * This struct exists just for convenience; we keep track of TB's in a binary
 499  * search tree, and the only fields needed to compare TB's in the tree are
 500  * @ptr and @size.
 501  * Note: the address of search data can be obtained by adding @size to @ptr.
 502  */
 503 struct tb_tc {
 504     const void *ptr;    /* pointer to the translated code */
 505     size_t size;
 506 };
 507
 508 struct TranslationBlock {
 509 #if !TARGET_TB_PCREL
 510     /*
 511      * Guest PC corresponding to this block.  This must be the true
 512      * virtual address.  Therefore e.g. x86 stores EIP + CS_BASE, and
 513      * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
 514      * privilege, must store those bits elsewhere.
 515      *
 516      * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
 517      * written such that the TB is associated only with the physical
 518      * page and may be run in any virtual address context.  In this case,
 519      * PC must always be taken from ENV in a target-specific manner.
 520      * Unwind information is taken as offsets from the page, to be
 521      * deposited into the "current" PC.
 522      */
 523     target_ulong pc;
 524 #endif
 525
 526     /*
 527      * Target-specific data associated with the TranslationBlock, e.g.:
 528      * x86: the original user, the Code Segment virtual base,
 529      * arm: an extension of tb->flags,
 530      * s390x: instruction data for EXECUTE,
 531      * sparc: the next pc of the instruction queue (for delay slots).
 532      */
 533     target_ulong cs_base;
 534
 535     uint32_t flags; /* flags defining in which context the code was generated */
 536     uint32_t cflags;    /* compile flags */
 537
 538 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */
 539 #define CF_COUNT_MASK    0x000001ff
 540 #define CF_NO_GOTO_TB    0x00000200 /* Do not chain with goto_tb */
 541 #define CF_NO_GOTO_PTR   0x00000400 /* Do not chain with goto_ptr */
 542 #define CF_SINGLE_STEP   0x00000800 /* gdbstub single-step in effect */
 543 #define CF_LAST_IO       0x00008000 /* Last insn may be an IO access.  */
 544 #define CF_MEMI_ONLY     0x00010000 /* Only instrument memory ops */
 545 #define CF_USE_ICOUNT    0x00020000
 546 #define CF_INVALID       0x00040000 /* TB is stale. Set with @jmp_lock held */
 547 #define CF_PARALLEL      0x00080000 /* Generate code for a parallel context */
 548 #define CF_NOIRQ         0x00100000 /* Generate an uninterruptible TB */
 549 #define CF_CLUSTER_MASK  0xff000000 /* Top 8 bits are cluster ID */
 550 #define CF_CLUSTER_SHIFT 24
 551
 552     /* Per-vCPU dynamic tracing state used to generate this TB */
 553     uint32_t trace_vcpu_dstate;
 554
 555     /*
 556      * Above fields used for comparing
 557      */
 558
 559     /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */
 560     uint16_t size;
 561     uint16_t icount;
 562
 563     struct tb_tc tc;
 564
 565     /*
 566      * Track tb_page_addr_t intervals that intersect this TB.
 567      * For user-only, the virtual addresses are always contiguous,
 568      * and we use a unified interval tree.  For system, we use a
 569      * linked list headed in each PageDesc.  Within the list, the lsb
 570      * of the previous pointer tells the index of page_next[], and the
 571      * list is protected by the PageDesc lock(s).
 572      */
 573 #ifdef CONFIG_USER_ONLY
 574     IntervalTreeNode itree;
 575 #else
 576     uintptr_t page_next[2];
 577     tb_page_addr_t page_addr[2];
 578 #endif
 579
 580     /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
 581     QemuSpin jmp_lock;
 582
 583     /* The following data are used to directly call another TB from
 584      * the code of this one. This can be done either by emitting direct or
 585      * indirect native jump instructions. These jumps are reset so that the TB
 586      * just continues its execution. The TB can be linked to another one by
 587      * setting one of the jump targets (or patching the jump instruction). Only
 588      * two of such jumps are supported.
 589      */
 590 #define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */
 591     uint16_t jmp_reset_offset[2]; /* offset of original jump target */
 592     uint16_t jmp_insn_offset[2];  /* offset of direct jump insn */
 593     uintptr_t jmp_target_addr[2]; /* target address */
 594
 595     /*
 596      * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
 597      * Each TB can have two outgoing jumps, and therefore can participate
 598      * in two lists. The list entries are kept in jmp_list_next[2]. The least
 599      * significant bit (LSB) of the pointers in these lists is used to encode
 600      * which of the two list entries is to be used in the pointed TB.
 601      *
 602      * List traversals are protected by jmp_lock. The destination TB of each
 603      * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
 604      * can be acquired from any origin TB.
 605      *
 606      * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
 607      * being invalidated, so that no further outgoing jumps from it can be set.
 608      *
 609      * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
 610      * to a destination TB that has CF_INVALID set.
 611      */
 612     uintptr_t jmp_list_head;
 613     uintptr_t jmp_list_next[2];
 614     uintptr_t jmp_dest[2];
 615 };
 616
 617 /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
 618 static inline target_ulong tb_pc(const TranslationBlock *tb)
 619 {
 620 #if TARGET_TB_PCREL
 621     qemu_build_not_reached();
 622 #else
 623     return tb->pc;
 624 #endif
 625 }
 626
 627 /* Hide the qatomic_read to make code a little easier on the eyes */
 628 static inline uint32_t tb_cflags(const TranslationBlock *tb)
 629 {
 630     return qatomic_read(&tb->cflags);
 631 }
 632
 633 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
 634 {
 635 #ifdef CONFIG_USER_ONLY
 636     return tb->itree.start;
 637 #else
 638     return tb->page_addr[0];
 639 #endif
 640 }
 641
 642 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb)
 643 {
 644 #ifdef CONFIG_USER_ONLY
 645     tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK;
 646     return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next;
 647 #else
 648     return tb->page_addr[1];
 649 #endif
 650 }
 651
 652 static inline void tb_set_page_addr0(TranslationBlock *tb,
 653                                      tb_page_addr_t addr)
 654 {
 655 #ifdef CONFIG_USER_ONLY
 656     tb->itree.start = addr;
 657     /*
 658      * To begin, we record an interval of one byte.  When the translation
 659      * loop encounters a second page, the interval will be extended to
 660      * include the first byte of the second page, which is sufficient to
 661      * allow tb_page_addr1() above to work properly.  The final corrected
 662      * interval will be set by tb_page_add() from tb->size before the
 663      * node is added to the interval tree.
 664      */
 665     tb->itree.last = addr;
 666 #else
 667     tb->page_addr[0] = addr;
 668 #endif
 669 }
 670
 671 static inline void tb_set_page_addr1(TranslationBlock *tb,
 672                                      tb_page_addr_t addr)
 673 {
 674 #ifdef CONFIG_USER_ONLY
 675     /* Extend the interval to the first byte of the second page.  See above. */
 676     tb->itree.last = addr;
 677 #else
 678     tb->page_addr[1] = addr;
 679 #endif
 680 }
 681
 682 /* current cflags for hashing/comparison */
 683 uint32_t curr_cflags(CPUState *cpu);
 684
 685 /* TranslationBlock invalidate API */
 686 #if defined(CONFIG_USER_ONLY)
 687 void tb_invalidate_phys_addr(target_ulong addr);
 688 #else
 689 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 690 #endif
 691 void tb_flush(CPUState *cpu);
 692 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 693 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end);
 694 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
 695
 696 /* GETPC is the true target of the return instruction that we'll execute.  */
 697 #if defined(CONFIG_TCG_INTERPRETER)
 698 extern __thread uintptr_t tci_tb_ptr;
 699 # define GETPC() tci_tb_ptr
 700 #else
 701 # define GETPC() \
 702     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 703 #endif
 704
 705 /* The true return address will often point to a host insn that is part of
 706    the next translated guest insn.  Adjust the address backward to point to
 707    the middle of the call insn.  Subtracting one would do the job except for
 708    several compressed mode architectures (arm, mips) which set the low bit
 709    to indicate the compressed mode; subtracting two works around that.  It
 710    is also the case that there are no host isas that contain a call insn
 711    smaller than 4 bytes, so we don't worry about special-casing this.  */
 712 #define GETPC_ADJ   2
 713
 714 #if !defined(CONFIG_USER_ONLY)
 715
 716 /**
 717  * iotlb_to_section:
 718  * @cpu: CPU performing the access
 719  * @index: TCG CPU IOTLB entry
 720  *
 721  * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
 722  * it refers to. @index will have been initially created and returned
 723  * by memory_region_section_get_iotlb().
 724  */
 725 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
 726                                              hwaddr index, MemTxAttrs attrs);
 727 #endif
 728
 729 /**
 730  * get_page_addr_code_hostp()
 731  * @env: CPUArchState
 732  * @addr: guest virtual address of guest code
 733  *
 734  * See get_page_addr_code() (full-system version) for documentation on the
 735  * return value.
 736  *
 737  * Sets *@hostp (when @hostp is non-NULL) as follows.
 738  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
 739  * to the host address where @addr's content is kept.
 740  *
 741  * Note: this function can trigger an exception.
 742  */
 743 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
 744                                         void **hostp);
 745
 746 /**
 747  * get_page_addr_code()
 748  * @env: CPUArchState
 749  * @addr: guest virtual address of guest code
 750  *
 751  * If we cannot translate and execute from the entire RAM page, or if
 752  * the region is not backed by RAM, returns -1. Otherwise, returns the
 753  * ram_addr_t corresponding to the guest code at @addr.
 754  *
 755  * Note: this function can trigger an exception.
 756  */
 757 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
 758                                                 target_ulong addr)
 759 {
 760     return get_page_addr_code_hostp(env, addr, NULL);
 761 }
 762
 763 #if defined(CONFIG_USER_ONLY)
 764 void TSA_NO_TSA mmap_lock(void);
 765 void TSA_NO_TSA mmap_unlock(void);
 766 bool have_mmap_lock(void);
 767
 768 /**
 769  * adjust_signal_pc:
 770  * @pc: raw pc from the host signal ucontext_t.
 771  * @is_write: host memory operation was write, or read-modify-write.
 772  *
 773  * Alter @pc as required for unwinding.  Return the type of the
 774  * guest memory access -- host reads may be for guest execution.
 775  */
 776 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
 777
 778 /**
 779  * handle_sigsegv_accerr_write:
 780  * @cpu: the cpu context
 781  * @old_set: the sigset_t from the signal ucontext_t
 782  * @host_pc: the host pc, adjusted for the signal
 783  * @host_addr: the host address of the fault
 784  *
 785  * Return true if the write fault has been handled, and should be re-tried.
 786  */
 787 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
 788                                  uintptr_t host_pc, abi_ptr guest_addr);
 789
 790 /**
 791  * cpu_loop_exit_sigsegv:
 792  * @cpu: the cpu context
 793  * @addr: the guest address of the fault
 794  * @access_type: access was read/write/execute
 795  * @maperr: true for invalid page, false for permission fault
 796  * @ra: host pc for unwinding
 797  *
 798  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 799  * specific things to raise SIGSEGV, and jump to the main cpu loop.
 800  */
 801 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
 802                                       MMUAccessType access_type,
 803                                       bool maperr, uintptr_t ra);
 804
 805 /**
 806  * cpu_loop_exit_sigbus:
 807  * @cpu: the cpu context
 808  * @addr: the guest address of the alignment fault
 809  * @access_type: access was read/write/execute
 810  * @ra: host pc for unwinding
 811  *
 812  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 813  * specific things to raise SIGBUS, and jump to the main cpu loop.
 814  */
 815 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
 816                                      MMUAccessType access_type,
 817                                      uintptr_t ra);
 818
 819 #else
 820 static inline void mmap_lock(void) {}
 821 static inline void mmap_unlock(void) {}
 822
 823 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 824 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 825
 826 MemoryRegionSection *
 827 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 828                                   hwaddr *xlat, hwaddr *plen,
 829                                   MemTxAttrs attrs, int *prot);
 830 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 831                                        MemoryRegionSection *section);
 832 #endif
 833
 834 #endif