include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef EXEC_ALL_H
  21 #define EXEC_ALL_H
  22
  23 #include "cpu.h"
  24 #ifdef CONFIG_TCG
  25 #include "exec/cpu_ldst.h"
  26 #endif
  27
  28 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  29 #define DEBUG_DISAS
  30
  31 /* Page tracking code uses ram addresses in system mode, and virtual
  32    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  33    type.  */
  34 #if defined(CONFIG_USER_ONLY)
  35 typedef abi_ulong tb_page_addr_t;
  36 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
  37 #else
  38 typedef ram_addr_t tb_page_addr_t;
  39 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
  40 #endif
  41
  42 void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
  43                           target_ulong *data);
  44
  45 /**
  46  * cpu_restore_state:
  47  * @cpu: the vCPU state is to be restore to
  48  * @searched_pc: the host PC the fault occurred at
  49  * @will_exit: true if the TB executed will be interrupted after some
  50                cpu adjustments. Required for maintaining the correct
  51                icount valus
  52  * @return: true if state was restored, false otherwise
  53  *
  54  * Attempt to restore the state for a fault occurring in translated
  55  * code. If the searched_pc is not in translated code no state is
  56  * restored and the function returns false.
  57  */
  58 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
  59
  60 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
  61 G_NORETURN void cpu_loop_exit(CPUState *cpu);
  62 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  63 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
  64
  65 /**
  66  * cpu_loop_exit_requested:
  67  * @cpu: The CPU state to be tested
  68  *
  69  * Indicate if somebody asked for a return of the CPU to the main loop
  70  * (e.g., via cpu_exit() or cpu_interrupt()).
  71  *
  72  * This is helpful for architectures that support interruptible
  73  * instructions. After writing back all state to registers/memory, this
  74  * call can be used to check if it makes sense to return to the main loop
  75  * or to continue executing the interruptible instruction.
  76  */
  77 static inline bool cpu_loop_exit_requested(CPUState *cpu)
  78 {
  79     return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0;
  80 }
  81
  82 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  83 /* cputlb.c */
  84 /**
  85  * tlb_init - initialize a CPU's TLB
  86  * @cpu: CPU whose TLB should be initialized
  87  */
  88 void tlb_init(CPUState *cpu);
  89 /**
  90  * tlb_destroy - destroy a CPU's TLB
  91  * @cpu: CPU whose TLB should be destroyed
  92  */
  93 void tlb_destroy(CPUState *cpu);
  94 /**
  95  * tlb_flush_page:
  96  * @cpu: CPU whose TLB should be flushed
  97  * @addr: virtual address of page to be flushed
  98  *
  99  * Flush one page from the TLB of the specified CPU, for all
 100  * MMU indexes.
 101  */
 102 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 103 /**
 104  * tlb_flush_page_all_cpus:
 105  * @cpu: src CPU of the flush
 106  * @addr: virtual address of page to be flushed
 107  *
 108  * Flush one page from the TLB of the specified CPU, for all
 109  * MMU indexes.
 110  */
 111 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
 112 /**
 113  * tlb_flush_page_all_cpus_synced:
 114  * @cpu: src CPU of the flush
 115  * @addr: virtual address of page to be flushed
 116  *
 117  * Flush one page from the TLB of the specified CPU, for all MMU
 118  * indexes like tlb_flush_page_all_cpus except the source vCPUs work
 119  * is scheduled as safe work meaning all flushes will be complete once
 120  * the source vCPUs safe work is complete. This will depend on when
 121  * the guests translation ends the TB.
 122  */
 123 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
 124 /**
 125  * tlb_flush:
 126  * @cpu: CPU whose TLB should be flushed
 127  *
 128  * Flush the entire TLB for the specified CPU. Most CPU architectures
 129  * allow the implementation to drop entries from the TLB at any time
 130  * so this is generally safe. If more selective flushing is required
 131  * use one of the other functions for efficiency.
 132  */
 133 void tlb_flush(CPUState *cpu);
 134 /**
 135  * tlb_flush_all_cpus:
 136  * @cpu: src CPU of the flush
 137  */
 138 void tlb_flush_all_cpus(CPUState *src_cpu);
 139 /**
 140  * tlb_flush_all_cpus_synced:
 141  * @cpu: src CPU of the flush
 142  *
 143  * Like tlb_flush_all_cpus except this except the source vCPUs work is
 144  * scheduled as safe work meaning all flushes will be complete once
 145  * the source vCPUs safe work is complete. This will depend on when
 146  * the guests translation ends the TB.
 147  */
 148 void tlb_flush_all_cpus_synced(CPUState *src_cpu);
 149 /**
 150  * tlb_flush_page_by_mmuidx:
 151  * @cpu: CPU whose TLB should be flushed
 152  * @addr: virtual address of page to be flushed
 153  * @idxmap: bitmap of MMU indexes to flush
 154  *
 155  * Flush one page from the TLB of the specified CPU, for the specified
 156  * MMU indexes.
 157  */
 158 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
 159                               uint16_t idxmap);
 160 /**
 161  * tlb_flush_page_by_mmuidx_all_cpus:
 162  * @cpu: Originating CPU of the flush
 163  * @addr: virtual address of page to be flushed
 164  * @idxmap: bitmap of MMU indexes to flush
 165  *
 166  * Flush one page from the TLB of all CPUs, for the specified
 167  * MMU indexes.
 168  */
 169 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 170                                        uint16_t idxmap);
 171 /**
 172  * tlb_flush_page_by_mmuidx_all_cpus_synced:
 173  * @cpu: Originating CPU of the flush
 174  * @addr: virtual address of page to be flushed
 175  * @idxmap: bitmap of MMU indexes to flush
 176  *
 177  * Flush one page from the TLB of all CPUs, for the specified MMU
 178  * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
 179  * vCPUs work is scheduled as safe work meaning all flushes will be
 180  * complete once  the source vCPUs safe work is complete. This will
 181  * depend on when the guests translation ends the TB.
 182  */
 183 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 184                                               uint16_t idxmap);
 185 /**
 186  * tlb_flush_by_mmuidx:
 187  * @cpu: CPU whose TLB should be flushed
 188  * @wait: If true ensure synchronisation by exiting the cpu_loop
 189  * @idxmap: bitmap of MMU indexes to flush
 190  *
 191  * Flush all entries from the TLB of the specified CPU, for the specified
 192  * MMU indexes.
 193  */
 194 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
 195 /**
 196  * tlb_flush_by_mmuidx_all_cpus:
 197  * @cpu: Originating CPU of the flush
 198  * @idxmap: bitmap of MMU indexes to flush
 199  *
 200  * Flush all entries from all TLBs of all CPUs, for the specified
 201  * MMU indexes.
 202  */
 203 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
 204 /**
 205  * tlb_flush_by_mmuidx_all_cpus_synced:
 206  * @cpu: Originating CPU of the flush
 207  * @idxmap: bitmap of MMU indexes to flush
 208  *
 209  * Flush all entries from all TLBs of all CPUs, for the specified
 210  * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
 211  * vCPUs work is scheduled as safe work meaning all flushes will be
 212  * complete once  the source vCPUs safe work is complete. This will
 213  * depend on when the guests translation ends the TB.
 214  */
 215 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
 216
 217 /**
 218  * tlb_flush_page_bits_by_mmuidx
 219  * @cpu: CPU whose TLB should be flushed
 220  * @addr: virtual address of page to be flushed
 221  * @idxmap: bitmap of mmu indexes to flush
 222  * @bits: number of significant bits in address
 223  *
 224  * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
 225  */
 226 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
 227                                    uint16_t idxmap, unsigned bits);
 228
 229 /* Similarly, with broadcast and syncing. */
 230 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 231                                             uint16_t idxmap, unsigned bits);
 232 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
 233     (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
 234
 235 /**
 236  * tlb_flush_range_by_mmuidx
 237  * @cpu: CPU whose TLB should be flushed
 238  * @addr: virtual address of the start of the range to be flushed
 239  * @len: length of range to be flushed
 240  * @idxmap: bitmap of mmu indexes to flush
 241  * @bits: number of significant bits in address
 242  *
 243  * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
 244  * comparing only the low @bits worth of each virtual page.
 245  */
 246 void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 247                                target_ulong len, uint16_t idxmap,
 248                                unsigned bits);
 249
 250 /* Similarly, with broadcast and syncing. */
 251 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 252                                         target_ulong len, uint16_t idxmap,
 253                                         unsigned bits);
 254 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 255                                                target_ulong addr,
 256                                                target_ulong len,
 257                                                uint16_t idxmap,
 258                                                unsigned bits);
 259
 260 /**
 261  * tlb_set_page_full:
 262  * @cpu: CPU context
 263  * @mmu_idx: mmu index of the tlb to modify
 264  * @vaddr: virtual address of the entry to add
 265  * @full: the details of the tlb entry
 266  *
 267  * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
 268  * @full must be filled, except for xlat_section, and constitute
 269  * the complete description of the translated page.
 270  *
 271  * This is generally called by the target tlb_fill function after
 272  * having performed a successful page table walk to find the physical
 273  * address and attributes for the translation.
 274  *
 275  * At most one entry for a given virtual address is permitted. Only a
 276  * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
 277  * used by tlb_flush_page.
 278  */
 279 void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
 280                        CPUTLBEntryFull *full);
 281
 282 /**
 283  * tlb_set_page_with_attrs:
 284  * @cpu: CPU to add this TLB entry for
 285  * @vaddr: virtual address of page to add entry for
 286  * @paddr: physical address of the page
 287  * @attrs: memory transaction attributes
 288  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 289  * @mmu_idx: MMU index to insert TLB entry for
 290  * @size: size of the page in bytes
 291  *
 292  * Add an entry to this CPU's TLB (a mapping from virtual address
 293  * @vaddr to physical address @paddr) with the specified memory
 294  * transaction attributes. This is generally called by the target CPU
 295  * specific code after it has been called through the tlb_fill()
 296  * entry point and performed a successful page table walk to find
 297  * the physical address and attributes for the virtual address
 298  * which provoked the TLB miss.
 299  *
 300  * At most one entry for a given virtual address is permitted. Only a
 301  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 302  * used by tlb_flush_page.
 303  */
 304 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 305                              hwaddr paddr, MemTxAttrs attrs,
 306                              int prot, int mmu_idx, target_ulong size);
 307 /* tlb_set_page:
 308  *
 309  * This function is equivalent to calling tlb_set_page_with_attrs()
 310  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 311  * as a convenience for CPUs which don't use memory transaction attributes.
 312  */
 313 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 314                   hwaddr paddr, int prot,
 315                   int mmu_idx, target_ulong size);
 316 #else
 317 static inline void tlb_init(CPUState *cpu)
 318 {
 319 }
 320 static inline void tlb_destroy(CPUState *cpu)
 321 {
 322 }
 323 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 324 {
 325 }
 326 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
 327 {
 328 }
 329 static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
 330                                                   target_ulong addr)
 331 {
 332 }
 333 static inline void tlb_flush(CPUState *cpu)
 334 {
 335 }
 336 static inline void tlb_flush_all_cpus(CPUState *src_cpu)
 337 {
 338 }
 339 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
 340 {
 341 }
 342 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 343                                             target_ulong addr, uint16_t idxmap)
 344 {
 345 }
 346
 347 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
 348 {
 349 }
 350 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
 351                                                      target_ulong addr,
 352                                                      uint16_t idxmap)
 353 {
 354 }
 355 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
 356                                                             target_ulong addr,
 357                                                             uint16_t idxmap)
 358 {
 359 }
 360 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
 361 {
 362 }
 363
 364 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
 365                                                        uint16_t idxmap)
 366 {
 367 }
 368 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
 369                                                  target_ulong addr,
 370                                                  uint16_t idxmap,
 371                                                  unsigned bits)
 372 {
 373 }
 374 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
 375                                                           target_ulong addr,
 376                                                           uint16_t idxmap,
 377                                                           unsigned bits)
 378 {
 379 }
 380 static inline void
 381 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 382                                               uint16_t idxmap, unsigned bits)
 383 {
 384 }
 385 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
 386                                              target_ulong len, uint16_t idxmap,
 387                                              unsigned bits)
 388 {
 389 }
 390 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
 391                                                       target_ulong addr,
 392                                                       target_ulong len,
 393                                                       uint16_t idxmap,
 394                                                       unsigned bits)
 395 {
 396 }
 397 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 398                                                              target_ulong addr,
 399                                                              target_long len,
 400                                                              uint16_t idxmap,
 401                                                              unsigned bits)
 402 {
 403 }
 404 #endif
 405 /**
 406  * probe_access:
 407  * @env: CPUArchState
 408  * @addr: guest virtual address to look up
 409  * @size: size of the access
 410  * @access_type: read, write or execute permission
 411  * @mmu_idx: MMU index to use for lookup
 412  * @retaddr: return address for unwinding
 413  *
 414  * Look up the guest virtual address @addr.  Raise an exception if the
 415  * page does not satisfy @access_type.  Raise an exception if the
 416  * access (@addr, @size) hits a watchpoint.  For writes, mark a clean
 417  * page as dirty.
 418  *
 419  * Finally, return the host address for a page that is backed by RAM,
 420  * or NULL if the page requires I/O.
 421  */
 422 void *probe_access(CPUArchState *env, target_ulong addr, int size,
 423                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 424
 425 static inline void *probe_write(CPUArchState *env, target_ulong addr, int size,
 426                                 int mmu_idx, uintptr_t retaddr)
 427 {
 428     return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
 429 }
 430
 431 static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
 432                                int mmu_idx, uintptr_t retaddr)
 433 {
 434     return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
 435 }
 436
 437 /**
 438  * probe_access_flags:
 439  * @env: CPUArchState
 440  * @addr: guest virtual address to look up
 441  * @access_type: read, write or execute permission
 442  * @mmu_idx: MMU index to use for lookup
 443  * @nonfault: suppress the fault
 444  * @phost: return value for host address
 445  * @retaddr: return address for unwinding
 446  *
 447  * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
 448  * the page, and storing the host address for RAM in @phost.
 449  *
 450  * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
 451  * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
 452  * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
 453  * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
 454  */
 455 int probe_access_flags(CPUArchState *env, target_ulong addr,
 456                        MMUAccessType access_type, int mmu_idx,
 457                        bool nonfault, void **phost, uintptr_t retaddr);
 458
 459 #ifndef CONFIG_USER_ONLY
 460 /**
 461  * probe_access_full:
 462  * Like probe_access_flags, except also return into @pfull.
 463  *
 464  * The CPUTLBEntryFull structure returned via @pfull is transient
 465  * and must be consumed or copied immediately, before any further
 466  * access or changes to TLB @mmu_idx.
 467  */
 468 int probe_access_full(CPUArchState *env, target_ulong addr,
 469                       MMUAccessType access_type, int mmu_idx,
 470                       bool nonfault, void **phost,
 471                       CPUTLBEntryFull **pfull, uintptr_t retaddr);
 472 #endif
 473
 474 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 475
 476 /* Estimated block size for TB allocation.  */
 477 /* ??? The following is based on a 2015 survey of x86_64 host output.
 478    Better would seem to be some sort of dynamically sized TB array,
 479    adapting to the block sizes actually being produced.  */
 480 #if defined(CONFIG_SOFTMMU)
 481 #define CODE_GEN_AVG_BLOCK_SIZE 400
 482 #else
 483 #define CODE_GEN_AVG_BLOCK_SIZE 150
 484 #endif
 485
 486 /*
 487  * Translation Cache-related fields of a TB.
 488  * This struct exists just for convenience; we keep track of TB's in a binary
 489  * search tree, and the only fields needed to compare TB's in the tree are
 490  * @ptr and @size.
 491  * Note: the address of search data can be obtained by adding @size to @ptr.
 492  */
 493 struct tb_tc {
 494     const void *ptr;    /* pointer to the translated code */
 495     size_t size;
 496 };
 497
 498 struct TranslationBlock {
 499 #if !TARGET_TB_PCREL
 500     /*
 501      * Guest PC corresponding to this block.  This must be the true
 502      * virtual address.  Therefore e.g. x86 stores EIP + CS_BASE, and
 503      * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
 504      * privilege, must store those bits elsewhere.
 505      *
 506      * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
 507      * written such that the TB is associated only with the physical
 508      * page and may be run in any virtual address context.  In this case,
 509      * PC must always be taken from ENV in a target-specific manner.
 510      * Unwind information is taken as offsets from the page, to be
 511      * deposited into the "current" PC.
 512      */
 513     target_ulong pc;
 514 #endif
 515
 516     /*
 517      * Target-specific data associated with the TranslationBlock, e.g.:
 518      * x86: the original user, the Code Segment virtual base,
 519      * arm: an extension of tb->flags,
 520      * s390x: instruction data for EXECUTE,
 521      * sparc: the next pc of the instruction queue (for delay slots).
 522      */
 523     target_ulong cs_base;
 524
 525     uint32_t flags; /* flags defining in which context the code was generated */
 526     uint32_t cflags;    /* compile flags */
 527
 528 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */
 529 #define CF_COUNT_MASK    0x000001ff
 530 #define CF_NO_GOTO_TB    0x00000200 /* Do not chain with goto_tb */
 531 #define CF_NO_GOTO_PTR   0x00000400 /* Do not chain with goto_ptr */
 532 #define CF_SINGLE_STEP   0x00000800 /* gdbstub single-step in effect */
 533 #define CF_LAST_IO       0x00008000 /* Last insn may be an IO access.  */
 534 #define CF_MEMI_ONLY     0x00010000 /* Only instrument memory ops */
 535 #define CF_USE_ICOUNT    0x00020000
 536 #define CF_INVALID       0x00040000 /* TB is stale. Set with @jmp_lock held */
 537 #define CF_PARALLEL      0x00080000 /* Generate code for a parallel context */
 538 #define CF_NOIRQ         0x00100000 /* Generate an uninterruptible TB */
 539 #define CF_CLUSTER_MASK  0xff000000 /* Top 8 bits are cluster ID */
 540 #define CF_CLUSTER_SHIFT 24
 541
 542     /* Per-vCPU dynamic tracing state used to generate this TB */
 543     uint32_t trace_vcpu_dstate;
 544
 545     /*
 546      * Above fields used for comparing
 547      */
 548
 549     /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */
 550     uint16_t size;
 551     uint16_t icount;
 552
 553     struct tb_tc tc;
 554
 555     /* first and second physical page containing code. The lower bit
 556        of the pointer tells the index in page_next[].
 557        The list is protected by the TB's page('s) lock(s) */
 558     uintptr_t page_next[2];
 559     tb_page_addr_t page_addr[2];
 560
 561     /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
 562     QemuSpin jmp_lock;
 563
 564     /* The following data are used to directly call another TB from
 565      * the code of this one. This can be done either by emitting direct or
 566      * indirect native jump instructions. These jumps are reset so that the TB
 567      * just continues its execution. The TB can be linked to another one by
 568      * setting one of the jump targets (or patching the jump instruction). Only
 569      * two of such jumps are supported.
 570      */
 571     uint16_t jmp_reset_offset[2]; /* offset of original jump target */
 572 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
 573     uintptr_t jmp_target_arg[2];  /* target address or offset */
 574
 575     /*
 576      * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
 577      * Each TB can have two outgoing jumps, and therefore can participate
 578      * in two lists. The list entries are kept in jmp_list_next[2]. The least
 579      * significant bit (LSB) of the pointers in these lists is used to encode
 580      * which of the two list entries is to be used in the pointed TB.
 581      *
 582      * List traversals are protected by jmp_lock. The destination TB of each
 583      * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
 584      * can be acquired from any origin TB.
 585      *
 586      * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
 587      * being invalidated, so that no further outgoing jumps from it can be set.
 588      *
 589      * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
 590      * to a destination TB that has CF_INVALID set.
 591      */
 592     uintptr_t jmp_list_head;
 593     uintptr_t jmp_list_next[2];
 594     uintptr_t jmp_dest[2];
 595 };
 596
 597 /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
 598 static inline target_ulong tb_pc(const TranslationBlock *tb)
 599 {
 600 #if TARGET_TB_PCREL
 601     qemu_build_not_reached();
 602 #else
 603     return tb->pc;
 604 #endif
 605 }
 606
 607 /* Hide the qatomic_read to make code a little easier on the eyes */
 608 static inline uint32_t tb_cflags(const TranslationBlock *tb)
 609 {
 610     return qatomic_read(&tb->cflags);
 611 }
 612
 613 /* current cflags for hashing/comparison */
 614 uint32_t curr_cflags(CPUState *cpu);
 615
 616 /* TranslationBlock invalidate API */
 617 #if defined(CONFIG_USER_ONLY)
 618 void tb_invalidate_phys_addr(target_ulong addr);
 619 void tb_invalidate_phys_range(target_ulong start, target_ulong end);
 620 #else
 621 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 622 #endif
 623 void tb_flush(CPUState *cpu);
 624 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 625 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
 626
 627 /* GETPC is the true target of the return instruction that we'll execute.  */
 628 #if defined(CONFIG_TCG_INTERPRETER)
 629 extern __thread uintptr_t tci_tb_ptr;
 630 # define GETPC() tci_tb_ptr
 631 #else
 632 # define GETPC() \
 633     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 634 #endif
 635
 636 /* The true return address will often point to a host insn that is part of
 637    the next translated guest insn.  Adjust the address backward to point to
 638    the middle of the call insn.  Subtracting one would do the job except for
 639    several compressed mode architectures (arm, mips) which set the low bit
 640    to indicate the compressed mode; subtracting two works around that.  It
 641    is also the case that there are no host isas that contain a call insn
 642    smaller than 4 bytes, so we don't worry about special-casing this.  */
 643 #define GETPC_ADJ   2
 644
 645 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG)
 646 void assert_no_pages_locked(void);
 647 #else
 648 static inline void assert_no_pages_locked(void)
 649 {
 650 }
 651 #endif
 652
 653 #if !defined(CONFIG_USER_ONLY)
 654
 655 /**
 656  * iotlb_to_section:
 657  * @cpu: CPU performing the access
 658  * @index: TCG CPU IOTLB entry
 659  *
 660  * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
 661  * it refers to. @index will have been initially created and returned
 662  * by memory_region_section_get_iotlb().
 663  */
 664 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
 665                                              hwaddr index, MemTxAttrs attrs);
 666 #endif
 667
 668 /**
 669  * get_page_addr_code_hostp()
 670  * @env: CPUArchState
 671  * @addr: guest virtual address of guest code
 672  *
 673  * See get_page_addr_code() (full-system version) for documentation on the
 674  * return value.
 675  *
 676  * Sets *@hostp (when @hostp is non-NULL) as follows.
 677  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
 678  * to the host address where @addr's content is kept.
 679  *
 680  * Note: this function can trigger an exception.
 681  */
 682 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
 683                                         void **hostp);
 684
 685 /**
 686  * get_page_addr_code()
 687  * @env: CPUArchState
 688  * @addr: guest virtual address of guest code
 689  *
 690  * If we cannot translate and execute from the entire RAM page, or if
 691  * the region is not backed by RAM, returns -1. Otherwise, returns the
 692  * ram_addr_t corresponding to the guest code at @addr.
 693  *
 694  * Note: this function can trigger an exception.
 695  */
 696 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
 697                                                 target_ulong addr)
 698 {
 699     return get_page_addr_code_hostp(env, addr, NULL);
 700 }
 701
 702 #if defined(CONFIG_USER_ONLY)
 703 void mmap_lock(void);
 704 void mmap_unlock(void);
 705 bool have_mmap_lock(void);
 706
 707 /**
 708  * adjust_signal_pc:
 709  * @pc: raw pc from the host signal ucontext_t.
 710  * @is_write: host memory operation was write, or read-modify-write.
 711  *
 712  * Alter @pc as required for unwinding.  Return the type of the
 713  * guest memory access -- host reads may be for guest execution.
 714  */
 715 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
 716
 717 /**
 718  * handle_sigsegv_accerr_write:
 719  * @cpu: the cpu context
 720  * @old_set: the sigset_t from the signal ucontext_t
 721  * @host_pc: the host pc, adjusted for the signal
 722  * @host_addr: the host address of the fault
 723  *
 724  * Return true if the write fault has been handled, and should be re-tried.
 725  */
 726 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
 727                                  uintptr_t host_pc, abi_ptr guest_addr);
 728
 729 /**
 730  * cpu_loop_exit_sigsegv:
 731  * @cpu: the cpu context
 732  * @addr: the guest address of the fault
 733  * @access_type: access was read/write/execute
 734  * @maperr: true for invalid page, false for permission fault
 735  * @ra: host pc for unwinding
 736  *
 737  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 738  * specific things to raise SIGSEGV, and jump to the main cpu loop.
 739  */
 740 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
 741                                       MMUAccessType access_type,
 742                                       bool maperr, uintptr_t ra);
 743
 744 /**
 745  * cpu_loop_exit_sigbus:
 746  * @cpu: the cpu context
 747  * @addr: the guest address of the alignment fault
 748  * @access_type: access was read/write/execute
 749  * @ra: host pc for unwinding
 750  *
 751  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 752  * specific things to raise SIGBUS, and jump to the main cpu loop.
 753  */
 754 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
 755                                      MMUAccessType access_type,
 756                                      uintptr_t ra);
 757
 758 #else
 759 static inline void mmap_lock(void) {}
 760 static inline void mmap_unlock(void) {}
 761
 762 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 763 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 764
 765 MemoryRegionSection *
 766 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 767                                   hwaddr *xlat, hwaddr *plen,
 768                                   MemTxAttrs attrs, int *prot);
 769 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 770                                        MemoryRegionSection *section);
 771 #endif
 772
 773 #endif