include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/cpu/a15mpcore.h"
  16 #include "hw/intc/aspeed_vic.h"
  17 #include "hw/misc/aspeed_scu.h"
  18 #include "hw/misc/aspeed_sdmc.h"
  19 #include "hw/misc/aspeed_xdma.h"
  20 #include "hw/timer/aspeed_timer.h"
  21 #include "hw/timer/aspeed_rtc.h"
  22 #include "hw/i2c/aspeed_i2c.h"
  23 #include "hw/ssi/aspeed_smc.h"
  24 #include "hw/watchdog/wdt_aspeed.h"
  25 #include "hw/net/ftgmac100.h"
  26 #include "target/arm/cpu.h"
  27 #include "hw/gpio/aspeed_gpio.h"
  28 #include "hw/sd/aspeed_sdhci.h"
  29
  30 #define ASPEED_SPIS_NUM  2
  31 #define ASPEED_WDTS_NUM  4
  32 #define ASPEED_CPUS_NUM  2
  33 #define ASPEED_MACS_NUM  2
  34
  35 typedef struct AspeedSoCState {
  36     /*< private >*/
  37     DeviceState parent;
  38
  39     /*< public >*/
  40     ARMCPU cpu[ASPEED_CPUS_NUM];
  41     uint32_t num_cpus;
  42     A15MPPrivState     a7mpcore;
  43     MemoryRegion sram;
  44     AspeedVICState vic;
  45     AspeedRtcState rtc;
  46     AspeedTimerCtrlState timerctrl;
  47     AspeedI2CState i2c;
  48     AspeedSCUState scu;
  49     AspeedXDMAState xdma;
  50     AspeedSMCState fmc;
  51     AspeedSMCState spi[ASPEED_SPIS_NUM];
  52     AspeedSDMCState sdmc;
  53     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  54     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  55     AspeedGPIOState gpio;
  56     AspeedGPIOState gpio_1_8v;
  57     AspeedSDHCIState sdhci;
  58 } AspeedSoCState;
  59
  60 #define TYPE_ASPEED_SOC "aspeed-soc"
  61 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
  62
  63 typedef struct AspeedSoCClass {
  64     DeviceClass parent_class;
  65
  66     const char *name;
  67     const char *cpu_type;
  68     uint32_t silicon_rev;
  69     uint64_t sram_size;
  70     int spis_num;
  71     int wdts_num;
  72     const int *irqmap;
  73     const hwaddr *memmap;
  74     uint32_t num_cpus;
  75 } AspeedSoCClass;
  76
  77 #define ASPEED_SOC_CLASS(klass)                                         \
  78     OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
  79 #define ASPEED_SOC_GET_CLASS(obj)                               \
  80     OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
  81
  82 enum {
  83     ASPEED_IOMEM,
  84     ASPEED_UART1,
  85     ASPEED_UART2,
  86     ASPEED_UART3,
  87     ASPEED_UART4,
  88     ASPEED_UART5,
  89     ASPEED_VUART,
  90     ASPEED_FMC,
  91     ASPEED_SPI1,
  92     ASPEED_SPI2,
  93     ASPEED_VIC,
  94     ASPEED_SDMC,
  95     ASPEED_SCU,
  96     ASPEED_ADC,
  97     ASPEED_SRAM,
  98     ASPEED_SDHCI,
  99     ASPEED_GPIO,
 100     ASPEED_GPIO_1_8V,
 101     ASPEED_RTC,
 102     ASPEED_TIMER1,
 103     ASPEED_TIMER2,
 104     ASPEED_TIMER3,
 105     ASPEED_TIMER4,
 106     ASPEED_TIMER5,
 107     ASPEED_TIMER6,
 108     ASPEED_TIMER7,
 109     ASPEED_TIMER8,
 110     ASPEED_WDT,
 111     ASPEED_PWM,
 112     ASPEED_LPC,
 113     ASPEED_IBT,
 114     ASPEED_I2C,
 115     ASPEED_ETH1,
 116     ASPEED_ETH2,
 117     ASPEED_SDRAM,
 118     ASPEED_XDMA,
 119 };
 120
 121 #endif /* ASPEED_SOC_H */