include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/intc/aspeed_vic.h"
  16 #include "hw/misc/aspeed_scu.h"
  17 #include "hw/misc/aspeed_sdmc.h"
  18 #include "hw/misc/aspeed_xdma.h"
  19 #include "hw/timer/aspeed_timer.h"
  20 #include "hw/timer/aspeed_rtc.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22 #include "hw/ssi/aspeed_smc.h"
  23 #include "hw/watchdog/wdt_aspeed.h"
  24 #include "hw/net/ftgmac100.h"
  25 #include "target/arm/cpu.h"
  26 #include "hw/gpio/aspeed_gpio.h"
  27
  28 #define ASPEED_SPIS_NUM  2
  29 #define ASPEED_WDTS_NUM  3
  30 #define ASPEED_CPUS_NUM  2
  31 #define ASPEED_MACS_NUM  2
  32
  33 typedef struct AspeedSoCState {
  34     /*< private >*/
  35     DeviceState parent;
  36
  37     /*< public >*/
  38     ARMCPU cpu[ASPEED_CPUS_NUM];
  39     uint32_t num_cpus;
  40     MemoryRegion sram;
  41     AspeedVICState vic;
  42     AspeedRtcState rtc;
  43     AspeedTimerCtrlState timerctrl;
  44     AspeedI2CState i2c;
  45     AspeedSCUState scu;
  46     AspeedXDMAState xdma;
  47     AspeedSMCState fmc;
  48     AspeedSMCState spi[ASPEED_SPIS_NUM];
  49     AspeedSDMCState sdmc;
  50     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  51     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  52     AspeedGPIOState gpio;
  53 } AspeedSoCState;
  54
  55 #define TYPE_ASPEED_SOC "aspeed-soc"
  56 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
  57
  58 typedef struct AspeedSoCInfo {
  59     const char *name;
  60     const char *cpu_type;
  61     uint32_t silicon_rev;
  62     uint64_t sram_size;
  63     int spis_num;
  64     const char *fmc_typename;
  65     const char **spi_typename;
  66     const char *gpio_typename;
  67     int wdts_num;
  68     const int *irqmap;
  69     const hwaddr *memmap;
  70     uint32_t num_cpus;
  71 } AspeedSoCInfo;
  72
  73 typedef struct AspeedSoCClass {
  74     DeviceClass parent_class;
  75     AspeedSoCInfo *info;
  76 } AspeedSoCClass;
  77
  78 #define ASPEED_SOC_CLASS(klass)                                         \
  79     OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
  80 #define ASPEED_SOC_GET_CLASS(obj)                               \
  81     OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
  82
  83 enum {
  84     ASPEED_IOMEM,
  85     ASPEED_UART1,
  86     ASPEED_UART2,
  87     ASPEED_UART3,
  88     ASPEED_UART4,
  89     ASPEED_UART5,
  90     ASPEED_VUART,
  91     ASPEED_FMC,
  92     ASPEED_SPI1,
  93     ASPEED_SPI2,
  94     ASPEED_VIC,
  95     ASPEED_SDMC,
  96     ASPEED_SCU,
  97     ASPEED_ADC,
  98     ASPEED_SRAM,
  99     ASPEED_GPIO,
 100     ASPEED_RTC,
 101     ASPEED_TIMER1,
 102     ASPEED_TIMER2,
 103     ASPEED_TIMER3,
 104     ASPEED_TIMER4,
 105     ASPEED_TIMER5,
 106     ASPEED_TIMER6,
 107     ASPEED_TIMER7,
 108     ASPEED_TIMER8,
 109     ASPEED_WDT,
 110     ASPEED_PWM,
 111     ASPEED_LPC,
 112     ASPEED_IBT,
 113     ASPEED_I2C,
 114     ASPEED_ETH1,
 115     ASPEED_ETH2,
 116     ASPEED_SDRAM,
 117     ASPEED_XDMA,
 118 };
 119
 120 #endif /* ASPEED_SOC_H */