include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/intc/aspeed_vic.h"
  16 #include "hw/misc/aspeed_scu.h"
  17 #include "hw/misc/aspeed_sdmc.h"
  18 #include "hw/misc/aspeed_xdma.h"
  19 #include "hw/timer/aspeed_timer.h"
  20 #include "hw/timer/aspeed_rtc.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22 #include "hw/ssi/aspeed_smc.h"
  23 #include "hw/watchdog/wdt_aspeed.h"
  24 #include "hw/net/ftgmac100.h"
  25 #include "target/arm/cpu.h"
  26 #include "hw/gpio/aspeed_gpio.h"
  27 #include "hw/sd/aspeed_sdhci.h"
  28
  29 #define ASPEED_SPIS_NUM  2
  30 #define ASPEED_WDTS_NUM  4
  31 #define ASPEED_CPUS_NUM  2
  32 #define ASPEED_MACS_NUM  2
  33
  34 typedef struct AspeedSoCState {
  35     /*< private >*/
  36     DeviceState parent;
  37
  38     /*< public >*/
  39     ARMCPU cpu[ASPEED_CPUS_NUM];
  40     uint32_t num_cpus;
  41     MemoryRegion sram;
  42     AspeedVICState vic;
  43     AspeedRtcState rtc;
  44     AspeedTimerCtrlState timerctrl;
  45     AspeedI2CState i2c;
  46     AspeedSCUState scu;
  47     AspeedXDMAState xdma;
  48     AspeedSMCState fmc;
  49     AspeedSMCState spi[ASPEED_SPIS_NUM];
  50     AspeedSDMCState sdmc;
  51     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  52     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  53     AspeedGPIOState gpio;
  54     AspeedSDHCIState sdhci;
  55 } AspeedSoCState;
  56
  57 #define TYPE_ASPEED_SOC "aspeed-soc"
  58 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
  59
  60 typedef struct AspeedSoCClass {
  61     DeviceClass parent_class;
  62
  63     const char *name;
  64     const char *cpu_type;
  65     uint32_t silicon_rev;
  66     uint64_t sram_size;
  67     int spis_num;
  68     int wdts_num;
  69     const int *irqmap;
  70     const hwaddr *memmap;
  71     uint32_t num_cpus;
  72 } AspeedSoCClass;
  73
  74 #define ASPEED_SOC_CLASS(klass)                                         \
  75     OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
  76 #define ASPEED_SOC_GET_CLASS(obj)                               \
  77     OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
  78
  79 enum {
  80     ASPEED_IOMEM,
  81     ASPEED_UART1,
  82     ASPEED_UART2,
  83     ASPEED_UART3,
  84     ASPEED_UART4,
  85     ASPEED_UART5,
  86     ASPEED_VUART,
  87     ASPEED_FMC,
  88     ASPEED_SPI1,
  89     ASPEED_SPI2,
  90     ASPEED_VIC,
  91     ASPEED_SDMC,
  92     ASPEED_SCU,
  93     ASPEED_ADC,
  94     ASPEED_SRAM,
  95     ASPEED_SDHCI,
  96     ASPEED_GPIO,
  97     ASPEED_RTC,
  98     ASPEED_TIMER1,
  99     ASPEED_TIMER2,
 100     ASPEED_TIMER3,
 101     ASPEED_TIMER4,
 102     ASPEED_TIMER5,
 103     ASPEED_TIMER6,
 104     ASPEED_TIMER7,
 105     ASPEED_TIMER8,
 106     ASPEED_WDT,
 107     ASPEED_PWM,
 108     ASPEED_LPC,
 109     ASPEED_IBT,
 110     ASPEED_I2C,
 111     ASPEED_ETH1,
 112     ASPEED_ETH2,
 113     ASPEED_SDRAM,
 114     ASPEED_XDMA,
 115 };
 116
 117 #endif /* ASPEED_SOC_H */