include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/cpu/a15mpcore.h"
  16 #include "hw/intc/aspeed_vic.h"
  17 #include "hw/misc/aspeed_scu.h"
  18 #include "hw/misc/aspeed_sdmc.h"
  19 #include "hw/misc/aspeed_xdma.h"
  20 #include "hw/timer/aspeed_timer.h"
  21 #include "hw/rtc/aspeed_rtc.h"
  22 #include "hw/i2c/aspeed_i2c.h"
  23 #include "hw/ssi/aspeed_smc.h"
  24 #include "hw/watchdog/wdt_aspeed.h"
  25 #include "hw/net/ftgmac100.h"
  26 #include "target/arm/cpu.h"
  27 #include "hw/gpio/aspeed_gpio.h"
  28 #include "hw/sd/aspeed_sdhci.h"
  29 #include "hw/usb/hcd-ehci.h"
  30
  31 #define ASPEED_SPIS_NUM  2
  32 #define ASPEED_EHCIS_NUM 2
  33 #define ASPEED_WDTS_NUM  4
  34 #define ASPEED_CPUS_NUM  2
  35 #define ASPEED_MACS_NUM  4
  36
  37 typedef struct AspeedSoCState {
  38     /*< private >*/
  39     DeviceState parent;
  40
  41     /*< public >*/
  42     ARMCPU cpu[ASPEED_CPUS_NUM];
  43     uint32_t num_cpus;
  44     A15MPPrivState     a7mpcore;
  45     MemoryRegion *dram_mr;
  46     MemoryRegion sram;
  47     AspeedVICState vic;
  48     AspeedRtcState rtc;
  49     AspeedTimerCtrlState timerctrl;
  50     AspeedI2CState i2c;
  51     AspeedSCUState scu;
  52     AspeedXDMAState xdma;
  53     AspeedSMCState fmc;
  54     AspeedSMCState spi[ASPEED_SPIS_NUM];
  55     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
  56     AspeedSDMCState sdmc;
  57     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  58     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  59     AspeedMiiState mii[ASPEED_MACS_NUM];
  60     AspeedGPIOState gpio;
  61     AspeedGPIOState gpio_1_8v;
  62     AspeedSDHCIState sdhci;
  63     AspeedSDHCIState emmc;
  64 } AspeedSoCState;
  65
  66 #define TYPE_ASPEED_SOC "aspeed-soc"
  67 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
  68
  69 typedef struct AspeedSoCClass {
  70     DeviceClass parent_class;
  71
  72     const char *name;
  73     const char *cpu_type;
  74     uint32_t silicon_rev;
  75     uint64_t sram_size;
  76     int spis_num;
  77     int ehcis_num;
  78     int wdts_num;
  79     int macs_num;
  80     const int *irqmap;
  81     const hwaddr *memmap;
  82     uint32_t num_cpus;
  83 } AspeedSoCClass;
  84
  85 #define ASPEED_SOC_CLASS(klass)                                         \
  86     OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
  87 #define ASPEED_SOC_GET_CLASS(obj)                               \
  88     OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
  89
  90 enum {
  91     ASPEED_IOMEM,
  92     ASPEED_UART1,
  93     ASPEED_UART2,
  94     ASPEED_UART3,
  95     ASPEED_UART4,
  96     ASPEED_UART5,
  97     ASPEED_VUART,
  98     ASPEED_FMC,
  99     ASPEED_SPI1,
 100     ASPEED_SPI2,
 101     ASPEED_EHCI1,
 102     ASPEED_EHCI2,
 103     ASPEED_VIC,
 104     ASPEED_SDMC,
 105     ASPEED_SCU,
 106     ASPEED_ADC,
 107     ASPEED_VIDEO,
 108     ASPEED_SRAM,
 109     ASPEED_SDHCI,
 110     ASPEED_GPIO,
 111     ASPEED_GPIO_1_8V,
 112     ASPEED_RTC,
 113     ASPEED_TIMER1,
 114     ASPEED_TIMER2,
 115     ASPEED_TIMER3,
 116     ASPEED_TIMER4,
 117     ASPEED_TIMER5,
 118     ASPEED_TIMER6,
 119     ASPEED_TIMER7,
 120     ASPEED_TIMER8,
 121     ASPEED_WDT,
 122     ASPEED_PWM,
 123     ASPEED_LPC,
 124     ASPEED_IBT,
 125     ASPEED_I2C,
 126     ASPEED_ETH1,
 127     ASPEED_ETH2,
 128     ASPEED_ETH3,
 129     ASPEED_ETH4,
 130     ASPEED_MII1,
 131     ASPEED_MII2,
 132     ASPEED_MII3,
 133     ASPEED_MII4,
 134     ASPEED_SDRAM,
 135     ASPEED_XDMA,
 136     ASPEED_EMMC,
 137 };
 138
 139 #endif /* ASPEED_SOC_H */