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1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/arm/arm.h"
16 #include "hw/intc/aspeed_vic.h"
17 #include "hw/misc/aspeed_scu.h"
18 #include "hw/misc/aspeed_sdmc.h"
19 #include "hw/timer/aspeed_timer.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "hw/ssi/aspeed_smc.h"
22 #include "hw/watchdog/wdt_aspeed.h"
23 #include "hw/net/ftgmac100.h"
24
25 #define ASPEED_SPIS_NUM 2
26 #define ASPEED_WDTS_NUM 3
27
28 typedef struct AspeedSoCState {
29 /*< private >*/
30 DeviceState parent;
31
32 /*< public >*/
33 ARMCPU cpu;
34 MemoryRegion sram;
35 AspeedVICState vic;
36 AspeedTimerCtrlState timerctrl;
37 AspeedI2CState i2c;
38 AspeedSCUState scu;
39 AspeedSMCState fmc;
40 AspeedSMCState spi[ASPEED_SPIS_NUM];
41 AspeedSDMCState sdmc;
42 AspeedWDTState wdt[ASPEED_WDTS_NUM];
43 FTGMAC100State ftgmac100;
44 } AspeedSoCState;
45
46 #define TYPE_ASPEED_SOC "aspeed-soc"
47 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
48
49 typedef struct AspeedSoCInfo {
50 const char *name;
51 const char *cpu_type;
52 uint32_t silicon_rev;
53 hwaddr sdram_base;
54 uint64_t sram_size;
55 int spis_num;
56 const hwaddr *spi_bases;
57 const char *fmc_typename;
58 const char **spi_typename;
59 int wdts_num;
60 } AspeedSoCInfo;
61
62 typedef struct AspeedSoCClass {
63 DeviceClass parent_class;
64 AspeedSoCInfo *info;
65 } AspeedSoCClass;
66
67 #define ASPEED_SOC_CLASS(klass) \
68 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
69 #define ASPEED_SOC_GET_CLASS(obj) \
70 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
71
72 #endif /* ASPEED_SOC_H */