2 * Samsung exynos4210 SoC emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
5 * Maksim Kozlov <m.kozlov@samsung.com>
6 * Evgeny Voevodin <e.voevodin@samsung.com>
7 * Igor Mitsyanko <i.mitsyanko@samsung.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 #include "hw/or-irq.h"
28 #include "hw/sysbus.h"
29 #include "hw/cpu/a9mpcore.h"
30 #include "hw/intc/exynos4210_gic.h"
31 #include "target/arm/cpu-qom.h"
32 #include "qom/object.h"
34 #define EXYNOS4210_NCPUS 2
36 #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
37 #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
38 #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
40 #define EXYNOS4210_IROM_BASE_ADDR 0x00000000
41 #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
42 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
43 #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
45 #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
46 #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
48 /* Secondary CPU startup code is in IROM memory */
49 #define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR
50 #define EXYNOS4210_SMP_BOOT_SIZE 0x1000
51 #define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR
52 /* Secondary CPU polling address to get loader start from */
53 #define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814
55 #define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000
56 #define EXYNOS4210_L2X0_BASE_ADDR 0x10502000
59 * exynos4210 IRQ subsystem stub definitions.
61 #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
63 #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64
64 #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16
65 #define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \
66 (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
67 #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
68 (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
70 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit))
71 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
72 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
73 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
75 /* IRQs number for external and internal GIC */
76 #define EXYNOS4210_EXT_GIC_NIRQ (160-32)
77 #define EXYNOS4210_INT_GIC_NIRQ 64
79 #define EXYNOS4210_I2C_NUMBER 9
81 #define EXYNOS4210_NUM_DMA 3
83 typedef struct Exynos4210Irq
{
84 qemu_irq int_combiner_irq
[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ
];
85 qemu_irq ext_combiner_irq
[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ
];
88 struct Exynos4210State
{
90 SysBusDevice parent_obj
;
92 ARMCPU
*cpu
[EXYNOS4210_NCPUS
];
94 qemu_irq irq_table
[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ
];
96 MemoryRegion chipid_mem
;
97 MemoryRegion iram_mem
;
98 MemoryRegion irom_mem
;
99 MemoryRegion irom_alias_mem
;
100 MemoryRegion boot_secondary
;
101 MemoryRegion bootreg_mem
;
102 I2CBus
*i2c_if
[EXYNOS4210_I2C_NUMBER
];
103 qemu_or_irq pl330_irq_orgate
[EXYNOS4210_NUM_DMA
];
104 qemu_or_irq cpu_irq_orgate
[EXYNOS4210_NCPUS
];
105 A9MPPrivState a9mpcore
;
106 Exynos4210GicState ext_gic
;
109 #define TYPE_EXYNOS4210_SOC "exynos4210"
110 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State
, EXYNOS4210_SOC
)
112 void exynos4210_write_secondary(ARMCPU
*cpu
,
113 const struct arm_boot_info
*info
);
115 /* Get IRQ number from exynos4210 IRQ subsystem stub.
116 * To identify IRQ source use internal combiner group and bit number
118 * bit - bit number inside group */
119 uint32_t exynos4210_get_irq(uint32_t grp
, uint32_t bit
);
122 * Get Combiner input GPIO into irqs structure
124 void exynos4210_combiner_get_gpioin(Exynos4210Irq
*irqs
, DeviceState
*dev
,
130 DeviceState
*exynos4210_uart_create(hwaddr addr
,
136 #endif /* EXYNOS4210_H */