include/hw/arm/fsl-imx7.h

   1 /*
   2  * Copyright (c) 2018, Impinj, Inc.
   3  *
   4  * i.MX7 SoC definitions
   5  *
   6  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #ifndef FSL_IMX7_H
  20 #define FSL_IMX7_H
  21
  22 #include "hw/arm/boot.h"
  23 #include "hw/cpu/a15mpcore.h"
  24 #include "hw/intc/imx_gpcv2.h"
  25 #include "hw/misc/imx7_ccm.h"
  26 #include "hw/misc/imx7_snvs.h"
  27 #include "hw/misc/imx7_gpr.h"
  28 #include "hw/misc/imx6_src.h"
  29 #include "hw/watchdog/wdt_imx2.h"
  30 #include "hw/gpio/imx_gpio.h"
  31 #include "hw/char/imx_serial.h"
  32 #include "hw/timer/imx_gpt.h"
  33 #include "hw/timer/imx_epit.h"
  34 #include "hw/i2c/imx_i2c.h"
  35 #include "hw/gpio/imx_gpio.h"
  36 #include "hw/sd/sdhci.h"
  37 #include "hw/ssi/imx_spi.h"
  38 #include "hw/net/imx_fec.h"
  39 #include "hw/pci-host/designware.h"
  40 #include "hw/usb/chipidea.h"
  41 #include "cpu.h"
  42 #include "qom/object.h"
  43
  44 #define TYPE_FSL_IMX7 "fsl,imx7"
  45 typedef struct FslIMX7State FslIMX7State;
  46 DECLARE_INSTANCE_CHECKER(FslIMX7State, FSL_IMX7,
  47                          TYPE_FSL_IMX7)
  48
  49 enum FslIMX7Configuration {
  50     FSL_IMX7_NUM_CPUS         = 2,
  51     FSL_IMX7_NUM_UARTS        = 7,
  52     FSL_IMX7_NUM_ETHS         = 2,
  53     FSL_IMX7_ETH_NUM_TX_RINGS = 3,
  54     FSL_IMX7_NUM_USDHCS       = 3,
  55     FSL_IMX7_NUM_WDTS         = 4,
  56     FSL_IMX7_NUM_GPTS         = 4,
  57     FSL_IMX7_NUM_IOMUXCS      = 2,
  58     FSL_IMX7_NUM_GPIOS        = 7,
  59     FSL_IMX7_NUM_I2CS         = 4,
  60     FSL_IMX7_NUM_ECSPIS       = 4,
  61     FSL_IMX7_NUM_USBS         = 3,
  62     FSL_IMX7_NUM_ADCS         = 2,
  63 };
  64
  65 struct FslIMX7State {
  66     /*< private >*/
  67     DeviceState    parent_obj;
  68
  69     /*< public >*/
  70     ARMCPU             cpu[FSL_IMX7_NUM_CPUS];
  71     A15MPPrivState     a7mpcore;
  72     IMXGPTState        gpt[FSL_IMX7_NUM_GPTS];
  73     IMXGPIOState       gpio[FSL_IMX7_NUM_GPIOS];
  74     IMX7CCMState       ccm;
  75     IMX7AnalogState    analog;
  76     IMX7SNVSState      snvs;
  77     IMXGPCv2State      gpcv2;
  78     IMXSPIState        spi[FSL_IMX7_NUM_ECSPIS];
  79     IMXI2CState        i2c[FSL_IMX7_NUM_I2CS];
  80     IMXSerialState     uart[FSL_IMX7_NUM_UARTS];
  81     IMXFECState        eth[FSL_IMX7_NUM_ETHS];
  82     SDHCIState         usdhc[FSL_IMX7_NUM_USDHCS];
  83     IMX2WdtState       wdt[FSL_IMX7_NUM_WDTS];
  84     IMX7GPRState       gpr;
  85     ChipideaState      usb[FSL_IMX7_NUM_USBS];
  86     DesignwarePCIEHost pcie;
  87     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
  88 };
  89
  90 enum FslIMX7MemoryMap {
  91     FSL_IMX7_MMDC_ADDR            = 0x80000000,
  92     FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
  93
  94     FSL_IMX7_GPIO1_ADDR           = 0x30200000,
  95     FSL_IMX7_GPIO2_ADDR           = 0x30210000,
  96     FSL_IMX7_GPIO3_ADDR           = 0x30220000,
  97     FSL_IMX7_GPIO4_ADDR           = 0x30230000,
  98     FSL_IMX7_GPIO5_ADDR           = 0x30240000,
  99     FSL_IMX7_GPIO6_ADDR           = 0x30250000,
 100     FSL_IMX7_GPIO7_ADDR           = 0x30260000,
 101
 102     FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
 103
 104     FSL_IMX7_WDOG1_ADDR           = 0x30280000,
 105     FSL_IMX7_WDOG2_ADDR           = 0x30290000,
 106     FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
 107     FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
 108
 109     FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
 110
 111     FSL_IMX7_GPT1_ADDR            = 0x302D0000,
 112     FSL_IMX7_GPT2_ADDR            = 0x302E0000,
 113     FSL_IMX7_GPT3_ADDR            = 0x302F0000,
 114     FSL_IMX7_GPT4_ADDR            = 0x30300000,
 115
 116     FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
 117     FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
 118     FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
 119
 120     FSL_IMX7_OCOTP_ADDR           = 0x30350000,
 121     FSL_IMX7_OCOTP_SIZE           = 0x10000,
 122
 123     FSL_IMX7_ANALOG_ADDR          = 0x30360000,
 124     FSL_IMX7_SNVS_ADDR            = 0x30370000,
 125     FSL_IMX7_CCM_ADDR             = 0x30380000,
 126
 127     FSL_IMX7_SRC_ADDR             = 0x30390000,
 128     FSL_IMX7_SRC_SIZE             = 0x1000,
 129
 130     FSL_IMX7_ADC1_ADDR            = 0x30610000,
 131     FSL_IMX7_ADC2_ADDR            = 0x30620000,
 132     FSL_IMX7_ADCn_SIZE            = 0x1000,
 133
 134     FSL_IMX7_PWM1_ADDR            = 0x30660000,
 135     FSL_IMX7_PWM2_ADDR            = 0x30670000,
 136     FSL_IMX7_PWM3_ADDR            = 0x30680000,
 137     FSL_IMX7_PWM4_ADDR            = 0x30690000,
 138     FSL_IMX7_PWMn_SIZE            = 0x10000,
 139
 140     FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
 141     FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
 142
 143     FSL_IMX7_GPC_ADDR             = 0x303A0000,
 144
 145     FSL_IMX7_CAAM_ADDR            = 0x30900000,
 146     FSL_IMX7_CAAM_SIZE            = 0x40000,
 147
 148     FSL_IMX7_CAN1_ADDR            = 0x30A00000,
 149     FSL_IMX7_CAN2_ADDR            = 0x30A10000,
 150     FSL_IMX7_CANn_SIZE            = 0x10000,
 151
 152     FSL_IMX7_I2C1_ADDR            = 0x30A20000,
 153     FSL_IMX7_I2C2_ADDR            = 0x30A30000,
 154     FSL_IMX7_I2C3_ADDR            = 0x30A40000,
 155     FSL_IMX7_I2C4_ADDR            = 0x30A50000,
 156
 157     FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
 158     FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
 159     FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
 160     FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
 161
 162     FSL_IMX7_LCDIF_ADDR           = 0x30730000,
 163     FSL_IMX7_LCDIF_SIZE           = 0x1000,
 164
 165     FSL_IMX7_UART1_ADDR           = 0x30860000,
 166     /*
 167      * Some versions of the reference manual claim that UART2 is @
 168      * 0x30870000, but experiments with HW + DT files in upstream
 169      * Linux kernel show that not to be true and that block is
 170      * acutally located @ 0x30890000
 171      */
 172     FSL_IMX7_UART2_ADDR           = 0x30890000,
 173     FSL_IMX7_UART3_ADDR           = 0x30880000,
 174     FSL_IMX7_UART4_ADDR           = 0x30A60000,
 175     FSL_IMX7_UART5_ADDR           = 0x30A70000,
 176     FSL_IMX7_UART6_ADDR           = 0x30A80000,
 177     FSL_IMX7_UART7_ADDR           = 0x30A90000,
 178
 179     FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 180     FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
 181
 182     FSL_IMX7_USB1_ADDR            = 0x30B10000,
 183     FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
 184     FSL_IMX7_USB2_ADDR            = 0x30B20000,
 185     FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
 186     FSL_IMX7_USB3_ADDR            = 0x30B30000,
 187     FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
 188     FSL_IMX7_USBMISCn_SIZE        = 0x200,
 189
 190     FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
 191     FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
 192     FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
 193
 194     FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
 195     FSL_IMX7_SDMA_SIZE            = 0x1000,
 196
 197     FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 198     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
 199
 200     FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 201     FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
 202
 203     FSL_IMX7_GPR_ADDR             = 0x30340000,
 204
 205     FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
 206     FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
 207 };
 208
 209 enum FslIMX7IRQs {
 210     FSL_IMX7_USDHC1_IRQ   = 22,
 211     FSL_IMX7_USDHC2_IRQ   = 23,
 212     FSL_IMX7_USDHC3_IRQ   = 24,
 213
 214     FSL_IMX7_UART1_IRQ    = 26,
 215     FSL_IMX7_UART2_IRQ    = 27,
 216     FSL_IMX7_UART3_IRQ    = 28,
 217     FSL_IMX7_UART4_IRQ    = 29,
 218     FSL_IMX7_UART5_IRQ    = 30,
 219     FSL_IMX7_UART6_IRQ    = 16,
 220
 221     FSL_IMX7_ECSPI1_IRQ   = 31,
 222     FSL_IMX7_ECSPI2_IRQ   = 32,
 223     FSL_IMX7_ECSPI3_IRQ   = 33,
 224     FSL_IMX7_ECSPI4_IRQ   = 34,
 225
 226     FSL_IMX7_I2C1_IRQ     = 35,
 227     FSL_IMX7_I2C2_IRQ     = 36,
 228     FSL_IMX7_I2C3_IRQ     = 37,
 229     FSL_IMX7_I2C4_IRQ     = 38,
 230
 231     FSL_IMX7_USB1_IRQ     = 43,
 232     FSL_IMX7_USB2_IRQ     = 42,
 233     FSL_IMX7_USB3_IRQ     = 40,
 234
 235     FSL_IMX7_WDOG1_IRQ    = 78,
 236     FSL_IMX7_WDOG2_IRQ    = 79,
 237     FSL_IMX7_WDOG3_IRQ    = 10,
 238     FSL_IMX7_WDOG4_IRQ    = 109,
 239
 240     FSL_IMX7_PCI_INTA_IRQ = 125,
 241     FSL_IMX7_PCI_INTB_IRQ = 124,
 242     FSL_IMX7_PCI_INTC_IRQ = 123,
 243     FSL_IMX7_PCI_INTD_IRQ = 122,
 244
 245     FSL_IMX7_UART7_IRQ    = 126,
 246
 247 #define FSL_IMX7_ENET_IRQ(i, n)  ((n) + ((i) ? 100 : 118))
 248
 249     FSL_IMX7_MAX_IRQ      = 128,
 250 };
 251
 252 #endif /* FSL_IMX7_H */