include/hw/arm/iotkit.h

   1 /*
   2  * ARM IoT Kit
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 /* This is a model of the Arm IoT Kit which is documented in
  13  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  14  * It contains:
  15  *  a Cortex-M33
  16  *  the IDAU
  17  *  some timers and watchdogs
  18  *  two peripheral protection controllers
  19  *  a memory protection controller
  20  *  a security controller
  21  *  a bus fabric which arranges that some parts of the address
  22  *  space are secure and non-secure aliases of each other
  23  *
  24  * QEMU interface:
  25  *  + QOM property "memory" is a MemoryRegion containing the devices provided
  26  *    by the board model.
  27  *  + QOM property "MAINCLK" is the frequency of the main system clock
  28  *  + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts
  29  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which
  30  *    are wired to the NVIC lines 32 .. n+32
  31  *  + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
  32  *    bus master devices in the board model to make transactions into
  33  *    all the devices and memory areas in the IoTKit
  34  * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
  35  * might provide:
  36  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
  37  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
  38  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
  39  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
  40  *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
  41  * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
  42  * might provide:
  43  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
  44  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
  45  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  46  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  47  *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
  48  * Controlling each of the 16 expansion MPCs which a system using the IoTKit
  49  * might provide:
  50  *  + named GPIO inputs mpcexp_status[0..15]
  51  * Controlling each of the 16 expansion MSCs which a system using the IoTKit
  52  * might provide:
  53  *  + named GPIO inputs mscexp_status[0..15]
  54  *  + named GPIO outputs mscexp_clear[0..15]
  55  *  + named GPIO outputs mscexp_ns[0..15]
  56  */
  57
  58 #ifndef IOTKIT_H
  59 #define IOTKIT_H
  60
  61 #include "hw/sysbus.h"
  62 #include "hw/arm/armv7m.h"
  63 #include "hw/misc/iotkit-secctl.h"
  64 #include "hw/misc/tz-ppc.h"
  65 #include "hw/misc/tz-mpc.h"
  66 #include "hw/timer/cmsdk-apb-timer.h"
  67 #include "hw/timer/cmsdk-apb-dualtimer.h"
  68 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  69 #include "hw/misc/iotkit-sysctl.h"
  70 #include "hw/misc/iotkit-sysinfo.h"
  71 #include "hw/or-irq.h"
  72 #include "hw/core/split-irq.h"
  73
  74 #define TYPE_IOTKIT "iotkit"
  75 #define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT)
  76
  77 /* We have an IRQ splitter and an OR gate input for each external PPC
  78  * and the 2 internal PPCs
  79  */
  80 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
  81 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
  82
  83 typedef struct IoTKit {
  84     /*< private >*/
  85     SysBusDevice parent_obj;
  86
  87     /*< public >*/
  88     ARMv7MState armv7m;
  89     IoTKitSecCtl secctl;
  90     TZPPC apb_ppc0;
  91     TZPPC apb_ppc1;
  92     TZMPC mpc;
  93     CMSDKAPBTIMER timer0;
  94     CMSDKAPBTIMER timer1;
  95     CMSDKAPBTIMER s32ktimer;
  96     qemu_or_irq ppc_irq_orgate;
  97     SplitIRQ sec_resp_splitter;
  98     SplitIRQ ppc_irq_splitter[NUM_PPCS];
  99     SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
 100     qemu_or_irq mpc_irq_orgate;
 101     qemu_or_irq nmi_orgate;
 102
 103     CMSDKAPBDualTimer dualtimer;
 104
 105     CMSDKAPBWatchdog s32kwatchdog;
 106     CMSDKAPBWatchdog nswatchdog;
 107     CMSDKAPBWatchdog swatchdog;
 108
 109     IoTKitSysCtl sysctl;
 110     IoTKitSysCtl sysinfo;
 111
 112     MemoryRegion container;
 113     MemoryRegion alias1;
 114     MemoryRegion alias2;
 115     MemoryRegion alias3;
 116     MemoryRegion sram0;
 117
 118     qemu_irq *exp_irqs;
 119     qemu_irq ppc0_irq;
 120     qemu_irq ppc1_irq;
 121     qemu_irq sec_resp_cfg;
 122     qemu_irq sec_resp_cfg_in;
 123     qemu_irq nsc_cfg_in;
 124
 125     qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
 126     qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
 127
 128     uint32_t nsccfg;
 129
 130     /* Properties */
 131     MemoryRegion *board_memory;
 132     uint32_t exp_numirq;
 133     uint32_t mainclk_frq;
 134 } IoTKit;
 135
 136 #endif